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c540769349
The Arm FVP documentation has grown organically over the years. As a
result, it has become a big document, which can be difficult to digest.
Also, the organization of some of the sections does not make sense. In
particular, all "Running on the ... FVP" sections live under a section
named "Booting a preloaded kernel image (Base FVP)". To illustrate this,
here is the current table of contents:
Arm Fixed Virtual Platforms (FVP)
Fixed Virtual Platform (FVP) Support
Arm FVP Platform Specific Build Options
Booting Firmware Update images
Booting an EL3 payload
Booting a preloaded kernel image (Base FVP)
Obtaining the Flattened Device Treesp
Running on the Foundation FVP with reset to BL1 entrypoint
Running on the AEMv8 Base FVP with reset to BL1 entrypoint
Running on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint
Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint
Running on the Cortex-A32 Base FVP (AArch32) with reset to BL1 entrypoint
Running on the AEMv8 Base FVP with reset to BL31 entrypoint
Running on the AEMv8 Base FVP (AArch32) with reset to SP_MIN entrypoint
Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint
Running on the Cortex-A32 Base FVP (AArch32) with reset to SP_MIN entrypoint
This patch breaks down this document in sub-documents, which are now
included from the index file. The table of contents (ToC) reflects the
new documents hierarchy. The depth of the ToC has been reduced to
simplify the index page. Here is what it looks like now:
Arm Fixed Virtual Platforms (FVP)
Fixed Virtual Platform (FVP) Support
Arm FVP Platform Specific Build Options
Running on the Foundation FVP
Running on the AEMv8 Base FVP
Running on the Cortex-A57-A53 Base FVP
Running on the Cortex-A32 Base FVP (AArch32)
Booting Firmware Update images
Booting an EL3 payload
Booting a preloaded kernel image (Base FVP)
Apart from moving information around in separate files, this patch also
makes the following minor changes to the contents:
- Add a brief introduction about FVPs in the index page.
- Change some of the titles names for conciseness.
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Icb650e0ec2c7a86ccd6e7eea4e16a84c41442c96
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7.5 KiB
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154 lines
7.5 KiB
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Running on the AEMv8 Base FVP
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=============================
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AArch64 with reset to BL1 entrypoint
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux
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with 8 CPUs using the AArch64 build of TF-A.
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.. code:: shell
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<path-to>/FVP_Base_RevC-2xAEMv8A \
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-C pctl.startup=0.0.0.0 \
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-C bp.secure_memory=1 \
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-C bp.tzc_400.diagnostics=1 \
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-C cluster0.NUM_CORES=4 \
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-C cluster1.NUM_CORES=4 \
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-C cache_state_modelled=1 \
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-C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
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-C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
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--data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
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--data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
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.. note::
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The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires
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a specific DTS for all the CPUs to be loaded.
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AArch32 with reset to BL1 entrypoint
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
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with 8 CPUs using the AArch32 build of TF-A.
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.. code:: shell
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<path-to>/FVP_Base_AEMv8A-AEMv8A \
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-C pctl.startup=0.0.0.0 \
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-C bp.secure_memory=1 \
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-C bp.tzc_400.diagnostics=1 \
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-C cluster0.NUM_CORES=4 \
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-C cluster1.NUM_CORES=4 \
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-C cache_state_modelled=1 \
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-C cluster0.cpu0.CONFIG64=0 \
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-C cluster0.cpu1.CONFIG64=0 \
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-C cluster0.cpu2.CONFIG64=0 \
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-C cluster0.cpu3.CONFIG64=0 \
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-C cluster1.cpu0.CONFIG64=0 \
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-C cluster1.cpu1.CONFIG64=0 \
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-C cluster1.cpu2.CONFIG64=0 \
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-C cluster1.cpu3.CONFIG64=0 \
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-C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
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-C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
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--data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
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--data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
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AArch64 with reset to BL31 entrypoint
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux
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with 8 CPUs using the AArch64 build of TF-A.
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.. code:: shell
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<path-to>/FVP_Base_RevC-2xAEMv8A \
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-C pctl.startup=0.0.0.0 \
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-C bp.secure_memory=1 \
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-C bp.tzc_400.diagnostics=1 \
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-C cluster0.NUM_CORES=4 \
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-C cluster1.NUM_CORES=4 \
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-C cache_state_modelled=1 \
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-C cluster0.cpu0.RVBAR=0x04010000 \
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-C cluster0.cpu1.RVBAR=0x04010000 \
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-C cluster0.cpu2.RVBAR=0x04010000 \
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-C cluster0.cpu3.RVBAR=0x04010000 \
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-C cluster1.cpu0.RVBAR=0x04010000 \
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-C cluster1.cpu1.RVBAR=0x04010000 \
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-C cluster1.cpu2.RVBAR=0x04010000 \
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-C cluster1.cpu3.RVBAR=0x04010000 \
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--data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \
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--data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \
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--data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
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--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
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--data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
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--data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
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Notes:
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- Position Independent Executable (PIE) support is enabled in this
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config allowing BL31 to be loaded at any valid address for execution.
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- Since a FIP is not loaded when using BL31 as reset entrypoint, the
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``--data="<path-to><bl31|bl32|bl33-binary>"@<base-address-of-binary>``
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parameter is needed to load the individual bootloader images in memory.
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BL32 image is only needed if BL31 has been built to expect a Secure-EL1
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Payload. For the same reason, the FDT needs to be compiled from the DT source
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and loaded via the ``--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000``
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parameter.
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- The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires a
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specific DTS for all the CPUs to be loaded.
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- The ``-C cluster<X>.cpu<Y>.RVBAR=@<base-address-of-bl31>`` parameter, where
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X and Y are the cluster and CPU numbers respectively, is used to set the
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reset vector for each core.
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- Changing the default value of ``ARM_TSP_RAM_LOCATION`` will also require
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changing the value of
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``--data="<path-to><bl32-binary>"@<base-address-of-bl32>`` to the new value of
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``BL32_BASE``.
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AArch32 with reset to SP_MIN entrypoint
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
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with 8 CPUs using the AArch32 build of TF-A.
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.. code:: shell
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<path-to>/FVP_Base_AEMv8A-AEMv8A \
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-C pctl.startup=0.0.0.0 \
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-C bp.secure_memory=1 \
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-C bp.tzc_400.diagnostics=1 \
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-C cluster0.NUM_CORES=4 \
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-C cluster1.NUM_CORES=4 \
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-C cache_state_modelled=1 \
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-C cluster0.cpu0.CONFIG64=0 \
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-C cluster0.cpu1.CONFIG64=0 \
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-C cluster0.cpu2.CONFIG64=0 \
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-C cluster0.cpu3.CONFIG64=0 \
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-C cluster1.cpu0.CONFIG64=0 \
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-C cluster1.cpu1.CONFIG64=0 \
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-C cluster1.cpu2.CONFIG64=0 \
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-C cluster1.cpu3.CONFIG64=0 \
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-C cluster0.cpu0.RVBAR=0x04002000 \
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-C cluster0.cpu1.RVBAR=0x04002000 \
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-C cluster0.cpu2.RVBAR=0x04002000 \
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-C cluster0.cpu3.RVBAR=0x04002000 \
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-C cluster1.cpu0.RVBAR=0x04002000 \
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-C cluster1.cpu1.RVBAR=0x04002000 \
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-C cluster1.cpu2.RVBAR=0x04002000 \
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-C cluster1.cpu3.RVBAR=0x04002000 \
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--data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \
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--data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
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--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
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--data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
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--data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
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.. note::
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Position Independent Executable (PIE) support is enabled in this
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config allowing SP_MIN to be loaded at any valid address for execution.
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--------------
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*Copyright (c) 2019-2024, Arm Limited. All rights reserved.*
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