mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
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e6a993d427
Add the support of AARCH32 in endian head file. The code is also
imported from FreeBSD 11.0. It's based on commit in below.
commit 4e3a5b429989b4ff621682ff1462f801237bd551
Author: mmel <mmel@FreeBSD.org>
Date: Tue Nov 10 12:02:41 2015 +0000
ARM: Remove trailing whitespace from sys/arm/include
No functional changes.
Approved by: kib (mentor)
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
168 lines
4.5 KiB
C
168 lines
4.5 KiB
C
/*-
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* Copyright (c) 2001 David E. O'Brien
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)endian.h 8.1 (Berkeley) 6/10/93
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* $NetBSD: endian.h,v 1.7 1999/08/21 05:53:51 simonb Exp $
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* $FreeBSD$
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*/
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/*
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* Portions copyright (c) 2017, ARM Limited and Contributors.
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* All rights reserved.
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*/
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#ifndef _MACHINE_ENDIAN_H_
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#define _MACHINE_ENDIAN_H_
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#include <sys/_types.h>
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/*
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* Definitions for byte order, according to byte significance from low
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* address to high.
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*/
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#define _LITTLE_ENDIAN 1234 /* LSB first: i386, vax */
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#define _BIG_ENDIAN 4321 /* MSB first: 68000, ibm, net */
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#define _PDP_ENDIAN 3412 /* LSB first in word, MSW first in long */
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#define _BYTE_ORDER _LITTLE_ENDIAN
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#if __BSD_VISIBLE
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#define LITTLE_ENDIAN _LITTLE_ENDIAN
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#define BIG_ENDIAN _BIG_ENDIAN
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#define PDP_ENDIAN _PDP_ENDIAN
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#define BYTE_ORDER _BYTE_ORDER
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#endif
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#define _QUAD_HIGHWORD 1
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#define _QUAD_LOWWORD 0
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#define __ntohl(x) (__bswap32(x))
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#define __ntohs(x) (__bswap16(x))
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#define __htonl(x) (__bswap32(x))
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#define __htons(x) (__bswap16(x))
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#ifdef AARCH32
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static __inline __uint64_t
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__bswap64(__uint64_t _x)
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{
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return ((_x >> 56) | ((_x >> 40) & 0xff00) | ((_x >> 24) & 0xff0000) |
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((_x >> 8) & 0xff000000) | ((_x << 8) & ((__uint64_t)0xff << 32)) |
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((_x << 24) & ((__uint64_t)0xff << 40)) |
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((_x << 40) & ((__uint64_t)0xff << 48)) | ((_x << 56)));
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}
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static __inline __uint32_t
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__bswap32_var(__uint32_t v)
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{
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__uint32_t t1;
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__asm __volatile("eor %1, %0, %0, ror #16\n"
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"bic %1, %1, #0x00ff0000\n"
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"mov %0, %0, ror #8\n"
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"eor %0, %0, %1, lsr #8\n"
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: "+r" (v), "=r" (t1));
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return (v);
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}
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static __inline __uint16_t
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__bswap16_var(__uint16_t v)
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{
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__uint32_t ret = v & 0xffff;
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__asm __volatile(
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"mov %0, %0, ror #8\n"
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"orr %0, %0, %0, lsr #16\n"
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"bic %0, %0, %0, lsl #16"
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: "+r" (ret));
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return ((__uint16_t)ret);
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}
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#elif defined AARCH64
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static __inline __uint64_t
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__bswap64(__uint64_t x)
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{
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__uint64_t ret;
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__asm __volatile("rev %0, %1\n"
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: "=&r" (ret), "+r" (x));
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return (ret);
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}
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static __inline __uint32_t
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__bswap32_var(__uint32_t v)
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{
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__uint32_t ret;
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__asm __volatile("rev32 %x0, %x1\n"
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: "=&r" (ret), "+r" (v));
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return (ret);
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}
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static __inline __uint16_t
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__bswap16_var(__uint16_t v)
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{
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__uint32_t ret;
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__asm __volatile("rev16 %w0, %w1\n"
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: "=&r" (ret), "+r" (v));
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return ((__uint16_t)ret);
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}
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#else
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#error "Only AArch32 or AArch64 supported"
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#endif /* AARCH32 */
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#ifdef __OPTIMIZE__
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#define __bswap32_constant(x) \
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((((x) & 0xff000000U) >> 24) | \
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(((x) & 0x00ff0000U) >> 8) | \
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(((x) & 0x0000ff00U) << 8) | \
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(((x) & 0x000000ffU) << 24))
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#define __bswap16_constant(x) \
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((((x) & 0xff00) >> 8) | \
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(((x) & 0x00ff) << 8))
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#define __bswap16(x) \
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((__uint16_t)(__builtin_constant_p(x) ? \
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__bswap16_constant(x) : \
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__bswap16_var(x)))
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#define __bswap32(x) \
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((__uint32_t)(__builtin_constant_p(x) ? \
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__bswap32_constant(x) : \
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__bswap32_var(x)))
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#else
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#define __bswap16(x) __bswap16_var(x)
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#define __bswap32(x) __bswap32_var(x)
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#endif /* __OPTIMIZE__ */
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#endif /* !_MACHINE_ENDIAN_H_ */
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