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https://github.com/ARM-software/arm-trusted-firmware.git
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0c8d4fef28
This patch disables routing of external aborts from lower exception levels to EL3 and ensures that a SError interrupt generated as a result of execution in EL3 is taken locally instead of a lower exception level. The SError interrupt is enabled in the TSP code only when the operation has not been directly initiated by the normal world. This is to prevent the possibility of an asynchronous external abort which originated in normal world from being taken when execution is in S-EL1. Fixes ARM-software/tf-issues#153 Change-Id: I157b996c75996d12fd86d27e98bc73dd8bce6cd5
213 lines
5.4 KiB
ArmAsm
213 lines
5.4 KiB
ArmAsm
/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <bl_common.h>
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#include <arch.h>
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#include <tsp.h>
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#include <asm_macros.S>
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/* ----------------------------------------------------
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* The caller-saved registers x0-x18 and LR are saved
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* here.
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* ----------------------------------------------------
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*/
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#define SCRATCH_REG_SIZE #(20 * 8)
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.macro save_caller_regs_and_lr
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sub sp, sp, SCRATCH_REG_SIZE
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stp x0, x1, [sp]
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stp x2, x3, [sp, #0x10]
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stp x4, x5, [sp, #0x20]
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stp x6, x7, [sp, #0x30]
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stp x8, x9, [sp, #0x40]
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stp x10, x11, [sp, #0x50]
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stp x12, x13, [sp, #0x60]
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stp x14, x15, [sp, #0x70]
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stp x16, x17, [sp, #0x80]
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stp x18, x30, [sp, #0x90]
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.endm
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.macro restore_caller_regs_and_lr
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ldp x0, x1, [sp]
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ldp x2, x3, [sp, #0x10]
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ldp x4, x5, [sp, #0x20]
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ldp x6, x7, [sp, #0x30]
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ldp x8, x9, [sp, #0x40]
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ldp x10, x11, [sp, #0x50]
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ldp x12, x13, [sp, #0x60]
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ldp x14, x15, [sp, #0x70]
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ldp x16, x17, [sp, #0x80]
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ldp x18, x30, [sp, #0x90]
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add sp, sp, SCRATCH_REG_SIZE
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.endm
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.globl tsp_exceptions
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/* -----------------------------------------------------
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* TSP exception handlers.
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* -----------------------------------------------------
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*/
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.section .vectors, "ax"; .align 11
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.align 7
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tsp_exceptions:
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/* -----------------------------------------------------
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* Current EL with _sp_el0 : 0x0 - 0x180. No exceptions
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* are expected and treated as irrecoverable errors.
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* -----------------------------------------------------
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*/
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sync_exception_sp_el0:
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wfi
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b sync_exception_sp_el0
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check_vector_size sync_exception_sp_el0
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.align 7
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irq_sp_el0:
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b irq_sp_el0
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check_vector_size irq_sp_el0
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.align 7
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fiq_sp_el0:
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b fiq_sp_el0
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check_vector_size fiq_sp_el0
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.align 7
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serror_sp_el0:
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b serror_sp_el0
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check_vector_size serror_sp_el0
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/* -----------------------------------------------------
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* Current EL with SPx: 0x200 - 0x380. Only IRQs/FIQs
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* are expected and handled
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* -----------------------------------------------------
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*/
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.align 7
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sync_exception_sp_elx:
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wfi
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b sync_exception_sp_elx
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check_vector_size sync_exception_sp_elx
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.align 7
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irq_sp_elx:
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/* Enable the SError interrupt */
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msr daifclr, #DAIF_ABT_BIT
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save_caller_regs_and_lr
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/* We just update some statistics in the handler */
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bl tsp_irq_received
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/* Hand over control to the normal world to handle the IRQ */
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smc #0
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/* The resume std smc starts from here */
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restore_caller_regs_and_lr
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eret
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check_vector_size irq_sp_elx
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.align 7
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fiq_sp_elx:
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/* Enable the SError interrupt */
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msr daifclr, #DAIF_ABT_BIT
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save_caller_regs_and_lr
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bl tsp_fiq_handler
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cbz x0, fiq_sp_elx_done
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/*
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* This FIQ was not targetted to S-EL1 so send it to
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* the monitor and wait for execution to resume.
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*/
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smc #0
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fiq_sp_elx_done:
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restore_caller_regs_and_lr
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eret
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check_vector_size fiq_sp_elx
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.align 7
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serror_sp_elx:
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b serror_sp_elx
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check_vector_size serror_sp_elx
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/* -----------------------------------------------------
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* Lower EL using AArch64 : 0x400 - 0x580. No exceptions
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* are handled since TSP does not implement a lower EL
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* -----------------------------------------------------
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*/
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.align 7
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sync_exception_aarch64:
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wfi
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b sync_exception_aarch64
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check_vector_size sync_exception_aarch64
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.align 7
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irq_aarch64:
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b irq_aarch64
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check_vector_size irq_aarch64
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.align 7
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fiq_aarch64:
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b fiq_aarch64
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check_vector_size fiq_aarch64
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.align 7
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serror_aarch64:
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b serror_aarch64
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check_vector_size serror_aarch64
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/* -----------------------------------------------------
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* Lower EL using AArch32 : 0x600 - 0x780. No exceptions
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* handled since the TSP does not implement a lower EL.
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* -----------------------------------------------------
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*/
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.align 7
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sync_exception_aarch32:
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wfi
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b sync_exception_aarch32
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check_vector_size sync_exception_aarch32
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.align 7
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irq_aarch32:
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b irq_aarch32
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check_vector_size irq_aarch32
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.align 7
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fiq_aarch32:
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b fiq_aarch32
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check_vector_size fiq_aarch32
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.align 7
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serror_aarch32:
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b serror_aarch32
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check_vector_size serror_aarch32
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.align 7
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