Achin Gupta 0c8d4fef28 Unmask SError interrupt and clear SCR_EL3.EA bit ... This patch disables routing of external aborts from lower exception levels to EL3 and ensures that a SError interrupt generated as a result of execution in EL3 is taken locally instead of a lower exception level. The SError interrupt is enabled in the TSP code only when the operation has not been directly initiated by the normal world. This is to prevent the possibility of an asynchronous external abort which originated in normal world from being taken when execution is in S-EL1. Fixes ARM-software/tf-issues#153 Change-Id: I157b996c75996d12fd86d27e98bc73dd8bce6cd5		2014-08-15 10:21:50 +01:00
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aarch64	Unmask SError interrupt and clear SCR_EL3.EA bit	2014-08-15 10:21:50 +01:00
bl31.ld.S	fvp: Reuse BL1 and BL2 memory through image overlaying	2014-07-10 16:34:54 +01:00
bl31.mk	Remove coherent stack usage from the warm boot path	2014-07-19 23:31:53 +01:00
bl31_main.c	Support asynchronous method for BL3-2 initialization	2014-08-01 09:48:07 +01:00
context_mgmt.c	Optimize EL3 register state stored in cpu_context structure	2014-07-31 10:09:58 +01:00
cpu_data_array.c	Rework the crash reporting in BL3-1 to use less stack	2014-07-28 11:03:20 +01:00
interrupt_mgmt.c	Rework incorrect use of assert() and panic() in codebase	2014-07-28 12:20:16 +01:00
runtime_svc.c	Remove all checkpatch errors from codebase	2014-06-24 12:50:00 +01:00