mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-18 02:24:18 +00:00
0c8d4fef28
This patch disables routing of external aborts from lower exception levels to EL3 and ensures that a SError interrupt generated as a result of execution in EL3 is taken locally instead of a lower exception level. The SError interrupt is enabled in the TSP code only when the operation has not been directly initiated by the normal world. This is to prevent the possibility of an asynchronous external abort which originated in normal world from being taken when execution is in S-EL1. Fixes ARM-software/tf-issues#153 Change-Id: I157b996c75996d12fd86d27e98bc73dd8bce6cd5
172 lines
5.9 KiB
ArmAsm
172 lines
5.9 KiB
ArmAsm
/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <asm_macros.S>
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.globl bl1_entrypoint
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/* -----------------------------------------------------
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* bl1_entrypoint() is the entry point into the trusted
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* firmware code when a cpu is released from warm or
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* cold reset.
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* -----------------------------------------------------
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*/
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func bl1_entrypoint
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/* ---------------------------------------------
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* Set the CPU endianness before doing anything
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* that might involve memory reads or writes.
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* ---------------------------------------------
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*/
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mrs x0, sctlr_el3
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bic x0, x0, #SCTLR_EE_BIT
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msr sctlr_el3, x0
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isb
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/* ---------------------------------------------
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* Perform any processor specific actions upon
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* reset e.g. cache, tlb invalidations etc.
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* ---------------------------------------------
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*/
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bl cpu_reset_handler
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/* ---------------------------------------------
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* Enable the instruction cache, stack pointer
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* and data access alignment checks
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* ---------------------------------------------
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*/
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mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
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mrs x0, sctlr_el3
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orr x0, x0, x1
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msr sctlr_el3, x0
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isb
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/* ---------------------------------------------
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* Set the exception vector to something sane.
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* ---------------------------------------------
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*/
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adr x0, bl1_exceptions
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msr vbar_el3, x0
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isb
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/* ---------------------------------------------
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* Enable the SError interrupt now that the
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* exception vectors have been setup.
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* ---------------------------------------------
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*/
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msr daifclr, #DAIF_ABT_BIT
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/* ---------------------------------------------------------------------
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* The initial state of the Architectural feature trap register
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* (CPTR_EL3) is unknown and it must be set to a known state. All
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* feature traps are disabled. Some bits in this register are marked as
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* Reserved and should not be modified.
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*
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* CPTR_EL3.TCPAC: This causes a direct access to the CPACR_EL1 from EL1
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* or the CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2.
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* CPTR_EL3.TTA: This causes access to the Trace functionality to trap
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* to EL3 when executed from EL0, EL1, EL2, or EL3. If system register
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* access to trace functionality is not supported, this bit is RES0.
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* CPTR_EL3.TFP: This causes instructions that access the registers
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* associated with Floating Point and Advanced SIMD execution to trap
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* to EL3 when executed from any exception level, unless trapped to EL1
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* or EL2.
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* ---------------------------------------------------------------------
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*/
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mrs x0, cptr_el3
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bic w0, w0, #TCPAC_BIT
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bic w0, w0, #TTA_BIT
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bic w0, w0, #TFP_BIT
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msr cptr_el3, x0
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/* -------------------------------------------------------
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* Will not return from this macro if it is a warm boot.
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* -------------------------------------------------------
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*/
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wait_for_entrypoint
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bl platform_mem_init
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/* ---------------------------------------------
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* Init C runtime environment.
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* - Zero-initialise the NOBITS sections.
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* There are 2 of them:
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* - the .bss section;
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* - the coherent memory section.
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* - Copy the data section from BL1 image
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* (stored in ROM) to the correct location
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* in RAM.
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* ---------------------------------------------
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*/
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ldr x0, =__BSS_START__
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ldr x1, =__BSS_SIZE__
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bl zeromem16
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ldr x0, =__COHERENT_RAM_START__
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ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__
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bl zeromem16
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ldr x0, =__DATA_RAM_START__
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ldr x1, =__DATA_ROM_START__
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ldr x2, =__DATA_SIZE__
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bl memcpy16
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/* --------------------------------------------
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* Allocate a stack whose memory will be marked
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* as Normal-IS-WBWA when the MMU is enabled.
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* There is no risk of reading stale stack
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* memory after enabling the MMU as only the
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* primary cpu is running at the moment.
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* --------------------------------------------
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*/
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mrs x0, mpidr_el1
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bl platform_set_stack
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/* ---------------------------------------------
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* Architectural init. can be generic e.g.
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* enabling stack alignment and platform spec-
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* ific e.g. MMU & page table setup as per the
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* platform memory map. Perform the latter here
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* and the former in bl1_main.
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* ---------------------------------------------
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*/
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bl bl1_early_platform_setup
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bl bl1_plat_arch_setup
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/* --------------------------------------------------
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* Initialize platform and jump to our c-entry point
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* for this type of reset. Panic if it returns
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* --------------------------------------------------
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*/
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bl bl1_main
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panic:
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b panic
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