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0bc3115f6e
In FFH mode, When handling nested serrors, serror is handled once and all subsequent serrors are considered handled.And EL3 directly return to lower EL. While returning to lower EL, x30 is restore to CTX_SAVED_GPREG_LR address.CTX_SAVED_GPREG_LR address belongs to EL3 address range and this address will not be accessible in lower EL. After return to lower EL, when lower EL access x30, segmentation fault happens and Kernel kills application. This patch restore x30 to lower EL address (CTX_GPREG_LR) to avoid segmentation fault at lower EL. Change-Id: Ie8becb206e0c0204e01d12ab63ae6e915dcf33e4 Signed-off-by: Jaiprakash Singh <jaiprakashs@marvell.com>
327 lines
8.6 KiB
ArmAsm
327 lines
8.6 KiB
ArmAsm
/*
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* Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2022, NVIDIA Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert_macros.S>
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#include <asm_macros.S>
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#include <assert_macros.S>
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#include <bl31/ea_handle.h>
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#include <context.h>
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#include <lib/extensions/ras_arch.h>
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#include <cpu_macros.S>
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#include <context.h>
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.globl handle_lower_el_sync_ea
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.globl handle_lower_el_async_ea
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.globl handle_pending_async_ea
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/*
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* This function handles Synchronous External Aborts from lower EL.
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*
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* It delegates the handling of the EA to platform handler, and upon successfully
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* handling the EA, exits EL3; otherwise panics.
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*
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* This function assumes x30 has been saved.
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*/
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func handle_lower_el_sync_ea
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mrs x30, esr_el3
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ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH
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/* Check for I/D aborts from lower EL */
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cmp x30, #EC_IABORT_LOWER_EL
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b.eq 1f
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cmp x30, #EC_DABORT_LOWER_EL
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b.eq 1f
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/* EA other than above are unhandled exceptions */
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no_ret report_unhandled_exception
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1:
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/*
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* Save general purpose and ARMv8.3-PAuth registers (if enabled).
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* Also save PMCR_EL0 and set the PSTATE to a known state.
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*/
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bl prepare_el3_entry
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#if ENABLE_PAUTH
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/* Load and program APIAKey firmware key */
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bl pauth_load_bl31_apiakey
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#endif
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/* Setup exception class and syndrome arguments for platform handler */
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mov x0, #ERROR_EA_SYNC
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mrs x1, esr_el3
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bl delegate_sync_ea
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/* el3_exit assumes SP_EL0 on entry */
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msr spsel, #MODE_SP_EL0
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b el3_exit
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endfunc handle_lower_el_sync_ea
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/*
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* This function handles SErrors from lower ELs.
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*
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* It delegates the handling of the EA to platform handler, and upon successfully
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* handling the EA, exits EL3; otherwise panics.
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*
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* This function assumes x30 has been saved.
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*/
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func handle_lower_el_async_ea
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/*
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* Save general purpose and ARMv8.3-PAuth registers (if enabled).
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* Also save PMCR_EL0 and set the PSTATE to a known state.
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*/
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bl prepare_el3_entry
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#if ENABLE_PAUTH
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/* Load and program APIAKey firmware key */
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bl pauth_load_bl31_apiakey
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#endif
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/* Setup exception class and syndrome arguments for platform handler */
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mov x0, #ERROR_EA_ASYNC
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mrs x1, esr_el3
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bl delegate_async_ea
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/* el3_exit assumes SP_EL0 on entry */
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msr spsel, #MODE_SP_EL0
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b el3_exit
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endfunc handle_lower_el_async_ea
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/*
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* Handler for async EA from lower EL synchronized at EL3 entry in FFH mode.
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*
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* This scenario may arise when there is an error (EA) in the system which is not
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* yet signaled to PE while executing in lower EL. During entry into EL3, the errors
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* are synchronized either implicitly or explicitly causing async EA to pend at EL3.
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*
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* On detecting the pending EA (via ISR_EL1.A), if the EA routing model is Firmware
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* First handling (FFH, SCR_EL3.EA = 1) this handler first handles the pending EA
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* and then handles the original exception.
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*
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* This function assumes x30 has been saved.
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*/
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func handle_pending_async_ea
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/*
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* Prepare for nested handling of EA. Stash sysregs clobbered by nested
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* exception and handler
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*/
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str x30, [sp, #CTX_EL3STATE_OFFSET + CTX_SAVED_GPREG_LR]
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mrs x30, esr_el3
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str x30, [sp, #CTX_EL3STATE_OFFSET + CTX_SAVED_ESR_EL3]
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mrs x30, spsr_el3
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str x30, [sp, #CTX_EL3STATE_OFFSET + CTX_SAVED_SPSR_EL3]
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mrs x30, elr_el3
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str x30, [sp, #CTX_EL3STATE_OFFSET + CTX_SAVED_ELR_EL3]
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mov x30, #1
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str x30, [sp, #CTX_EL3STATE_OFFSET + CTX_NESTED_EA_FLAG]
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/*
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* Restore the original x30 saved as part of entering EL3. This is not
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* required for the current function but for EL3 SError vector entry
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* once PSTATE.A bit is unmasked. We restore x30 and then the same
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* value is stored in EL3 SError vector entry.
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*/
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ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
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/*
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* After clearing PSTATE.A bit pending SError will trigger at current EL.
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* Put explicit synchronization event to ensure newly unmasked interrupt
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* is taken immediately.
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*/
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unmask_async_ea
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/* Restore the original exception information along with zeroing the storage */
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ldr x30, [sp, #CTX_EL3STATE_OFFSET + CTX_SAVED_ELR_EL3]
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msr elr_el3, x30
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str xzr, [sp, #CTX_EL3STATE_OFFSET + CTX_SAVED_ELR_EL3]
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ldr x30, [sp, #CTX_EL3STATE_OFFSET + CTX_SAVED_SPSR_EL3]
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msr spsr_el3, x30
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str xzr, [sp, #CTX_EL3STATE_OFFSET + CTX_SAVED_SPSR_EL3]
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ldr x30, [sp, #CTX_EL3STATE_OFFSET + CTX_SAVED_ESR_EL3]
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msr esr_el3, x30
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str xzr, [sp, #CTX_EL3STATE_OFFSET + CTX_SAVED_ESR_EL3]
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/*
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* If the original exception corresponds to SError from lower El, eret back
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* to lower EL, otherwise return to vector table for original exception handling.
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*/
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ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH
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cmp x30, #EC_SERROR
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ldr x30, [sp, #CTX_EL3STATE_OFFSET + CTX_SAVED_GPREG_LR]
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str xzr, [sp, #CTX_EL3STATE_OFFSET + CTX_SAVED_GPREG_LR]
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b.eq 1f
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ret
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1:
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ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
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str xzr, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
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exception_return
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endfunc handle_pending_async_ea
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/*
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* Prelude for Synchronous External Abort handling. This function assumes that
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* all GP registers have been saved by the caller.
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*
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* x0: EA reason
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* x1: EA syndrome
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*/
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func delegate_sync_ea
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#if ENABLE_FEAT_RAS
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/*
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* Check for Uncontainable error type. If so, route to the platform
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* fatal error handler rather than the generic EA one.
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*/
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ubfx x2, x1, #EABORT_SET_SHIFT, #EABORT_SET_WIDTH
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cmp x2, #ERROR_STATUS_SET_UC
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b.ne 1f
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/* Check fault status code */
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ubfx x3, x1, #EABORT_DFSC_SHIFT, #EABORT_DFSC_WIDTH
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cmp x3, #SYNC_EA_FSC
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b.ne 1f
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no_ret plat_handle_uncontainable_ea
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1:
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#endif
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b ea_proceed
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endfunc delegate_sync_ea
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/*
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* Prelude for Asynchronous External Abort handling. This function assumes that
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* all GP registers have been saved by the caller.
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*
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* x0: EA reason
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* x1: EA syndrome
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*/
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func delegate_async_ea
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#if ENABLE_FEAT_RAS
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/* Check Exception Class to ensure SError, as this function should
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* only be invoked for SError. If that is not the case, which implies
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* either an HW error or programming error, panic.
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*/
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ubfx x2, x1, #ESR_EC_SHIFT, #ESR_EC_LENGTH
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cmp x2, EC_SERROR
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b.ne el3_panic
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/*
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* Check for Implementation Defined Syndrome. If so, skip checking
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* Uncontainable error type from the syndrome as the format is unknown.
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*/
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tbnz x1, #SERROR_IDS_BIT, 1f
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/* AET only valid when DFSC is 0x11 */
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ubfx x2, x1, #EABORT_DFSC_SHIFT, #EABORT_DFSC_WIDTH
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cmp x2, #DFSC_SERROR
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b.ne 1f
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/*
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* Check for Uncontainable error type. If so, route to the platform
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* fatal error handler rather than the generic EA one.
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*/
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ubfx x3, x1, #EABORT_AET_SHIFT, #EABORT_AET_WIDTH
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cmp x3, #ERROR_STATUS_UET_UC
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b.ne 1f
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no_ret plat_handle_uncontainable_ea
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1:
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#endif
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b ea_proceed
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endfunc delegate_async_ea
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/*
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* Delegate External Abort handling to platform's EA handler. This function
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* assumes that all GP registers have been saved by the caller.
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*
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* x0: EA reason
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* x1: EA syndrome
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*/
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func ea_proceed
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/*
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* If the ESR loaded earlier is not zero, we were processing an EA
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* already, and this is a double fault.
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*/
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ldr x5, [sp, #CTX_EL3STATE_OFFSET + CTX_ESR_EL3]
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cbz x5, 1f
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no_ret plat_handle_double_fault
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1:
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/* Save EL3 state */
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mrs x2, spsr_el3
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mrs x3, elr_el3
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stp x2, x3, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
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/*
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* Save ESR as handling might involve lower ELs, and returning back to
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* EL3 from there would trample the original ESR.
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*/
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mrs x4, scr_el3
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mrs x5, esr_el3
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stp x4, x5, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
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/*
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* Setup rest of arguments, and call platform External Abort handler.
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*
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* x0: EA reason (already in place)
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* x1: Exception syndrome (already in place).
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* x2: Cookie (unused for now).
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* x3: Context pointer.
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* x4: Flags (security state from SCR for now).
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*/
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mov x2, xzr
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mov x3, sp
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ubfx x4, x4, #0, #1
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/* Switch to runtime stack */
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ldr x5, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
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msr spsel, #MODE_SP_EL0
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mov sp, x5
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mov x29, x30
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#if ENABLE_ASSERTIONS
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/* Stash the stack pointer */
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mov x28, sp
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#endif
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bl plat_ea_handler
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#if ENABLE_ASSERTIONS
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/*
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* Error handling flows might involve long jumps; so upon returning from
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* the platform error handler, validate that the we've completely
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* unwound the stack.
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*/
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mov x27, sp
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cmp x28, x27
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ASM_ASSERT(eq)
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#endif
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/* Make SP point to context */
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msr spsel, #MODE_SP_ELX
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/* Restore EL3 state and ESR */
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ldp x1, x2, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
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msr spsr_el3, x1
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msr elr_el3, x2
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/* Restore ESR_EL3 and SCR_EL3 */
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ldp x3, x4, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
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msr scr_el3, x3
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msr esr_el3, x4
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#if ENABLE_ASSERTIONS
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cmp x4, xzr
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ASM_ASSERT(ne)
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#endif
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/* Clear ESR storage */
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str xzr, [sp, #CTX_EL3STATE_OFFSET + CTX_ESR_EL3]
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ret x29
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endfunc ea_proceed
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