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0a580b5128
SVE and SME aren't enabled symmetrically for all worlds, but EL3 needs to context switch them nonetheless. Previously, this had to happen by writing the enable bits just before reading/writing the relevant context. But since the introduction of root context, this need not be the case. We can have these enables always be present for EL3 and save on some work (and ISBs!) on every context switch. We can also hoist ZCR_EL3 to a never changing register, as we set its value to be identical for every world, which happens to be the one we want for EL3 too. Change-Id: I3d950e72049a298008205ba32f230d5a5c02f8b0 Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
60 lines
1.6 KiB
C
60 lines
1.6 KiB
C
/*
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* Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdbool.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <lib/cassert.h>
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#include <lib/el3_runtime/pubsub.h>
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#include <lib/extensions/sve.h>
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CASSERT(SVE_VECTOR_LEN <= 2048, assert_sve_vl_too_long);
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CASSERT(SVE_VECTOR_LEN >= 128, assert_sve_vl_too_short);
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CASSERT((SVE_VECTOR_LEN % 128) == 0, assert_sve_vl_granule);
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/*
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* Converts SVE vector size restriction in bytes to LEN according to ZCR_EL3 documentation.
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* VECTOR_SIZE = (LEN+1) * 128
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*/
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#define CONVERT_SVE_LENGTH(x) (((x / 128) - 1))
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void sve_init_el3(void)
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{
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/* Restrict maximum SVE vector length (SVE_VECTOR_LEN+1) * 128. */
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write_zcr_el3(ZCR_EL3_LEN_MASK & CONVERT_SVE_LENGTH(SVE_VECTOR_LEN));
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}
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void sve_enable_per_world(per_world_context_t *per_world_ctx)
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{
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u_register_t cptr_el3;
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/* Enable access to SVE functionality for all ELs. */
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cptr_el3 = per_world_ctx->ctx_cptr_el3;
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cptr_el3 = (cptr_el3 | CPTR_EZ_BIT) & ~(TFP_BIT);
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per_world_ctx->ctx_cptr_el3 = cptr_el3;
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}
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void sve_init_el2_unused(void)
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{
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/*
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* CPTR_EL2.TFP: Set to zero so that Non-secure accesses to Advanced
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* SIMD and floating-point functionality from both Execution states do
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* not trap to EL2.
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*/
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write_cptr_el2(read_cptr_el2() & ~CPTR_EL2_TFP_BIT);
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}
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void sve_disable_per_world(per_world_context_t *per_world_ctx)
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{
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u_register_t reg;
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/* Disable SVE and FPU since they share registers. */
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reg = per_world_ctx->ctx_cptr_el3;
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reg &= ~CPTR_EZ_BIT; /* Trap SVE */
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reg |= TFP_BIT; /* Trap FPU/SIMD */
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per_world_ctx->ctx_cptr_el3 = reg;
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}
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