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0a580b5128
SVE and SME aren't enabled symmetrically for all worlds, but EL3 needs to context switch them nonetheless. Previously, this had to happen by writing the enable bits just before reading/writing the relevant context. But since the introduction of root context, this need not be the case. We can have these enables always be present for EL3 and save on some work (and ISBs!) on every context switch. We can also hoist ZCR_EL3 to a never changing register, as we set its value to be identical for every world, which happens to be the one we want for EL3 too. Change-Id: I3d950e72049a298008205ba32f230d5a5c02f8b0 Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
102 lines
2.4 KiB
C
102 lines
2.4 KiB
C
/*
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* Copyright (c) 2021-2025, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdbool.h>
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#include <arch.h>
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#include <arch_features.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <lib/el3_runtime/context_mgmt.h>
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#include <lib/extensions/sme.h>
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#include <lib/extensions/sve.h>
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void sme_enable(cpu_context_t *context)
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{
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u_register_t reg;
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el3_state_t *state;
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/* Get the context state. */
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state = get_el3state_ctx(context);
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/* Set the ENTP2 bit in SCR_EL3 to enable access to TPIDR2_EL0. */
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reg = read_ctx_reg(state, CTX_SCR_EL3);
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reg |= SCR_ENTP2_BIT;
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write_ctx_reg(state, CTX_SCR_EL3, reg);
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}
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void sme_enable_per_world(per_world_context_t *per_world_ctx)
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{
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u_register_t reg;
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/* Enable SME in CPTR_EL3. */
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reg = per_world_ctx->ctx_cptr_el3;
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reg |= ESM_BIT;
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per_world_ctx->ctx_cptr_el3 = reg;
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}
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void sme_init_el3(void)
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{
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u_register_t smcr_el3;
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/*
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* Set the max LEN value and FA64 bit. This register is set up per_world
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* to be the least restrictive, then lower ELs can restrict as needed
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* using SMCR_EL2 and SMCR_EL1.
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*/
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smcr_el3 = SMCR_ELX_LEN_MAX;
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if (is_feat_sme_fa64_present()) {
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VERBOSE("[SME] FA64 enabled\n");
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smcr_el3 |= SMCR_ELX_FA64_BIT;
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}
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/*
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* Enable access to ZT0 register.
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* Make sure FEAT_SME2 is supported by the hardware before continuing.
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* If supported, Set the EZT0 bit in SMCR_EL3 to allow instructions to
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* access ZT0 register without trapping.
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*/
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if (is_feat_sme2_supported()) {
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VERBOSE("SME2 enabled\n");
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smcr_el3 |= SMCR_ELX_EZT0_BIT;
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}
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write_smcr_el3(smcr_el3);
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}
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void sme_init_el2_unused(void)
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{
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/*
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* CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1 accesses to the
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* CPACR_EL1 or CPACR from both Execution states do not trap to EL2.
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*/
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write_cptr_el2(read_cptr_el2() & ~CPTR_EL2_TCPAC_BIT);
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}
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void sme_disable(cpu_context_t *context)
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{
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u_register_t reg;
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el3_state_t *state;
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/* Get the context state. */
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state = get_el3state_ctx(context);
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/* Disable access to TPIDR2_EL0. */
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reg = read_ctx_reg(state, CTX_SCR_EL3);
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reg &= ~SCR_ENTP2_BIT;
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write_ctx_reg(state, CTX_SCR_EL3, reg);
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}
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void sme_disable_per_world(per_world_context_t *per_world_ctx)
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{
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u_register_t reg;
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/* Disable SME, SVE, and FPU since they all share registers. */
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reg = per_world_ctx->ctx_cptr_el3;
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reg &= ~ESM_BIT; /* Trap SME */
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reg &= ~CPTR_EZ_BIT; /* Trap SVE */
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reg |= TFP_BIT; /* Trap FPU/SIMD */
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per_world_ctx->ctx_cptr_el3 = reg;
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}
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