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https://github.com/ARM-software/arm-trusted-firmware.git
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0a580b5128
SVE and SME aren't enabled symmetrically for all worlds, but EL3 needs to context switch them nonetheless. Previously, this had to happen by writing the enable bits just before reading/writing the relevant context. But since the introduction of root context, this need not be the case. We can have these enables always be present for EL3 and save on some work (and ISBs!) on every context switch. We can also hoist ZCR_EL3 to a never changing register, as we set its value to be identical for every world, which happens to be the one we want for EL3 too. Change-Id: I3d950e72049a298008205ba32f230d5a5c02f8b0 Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
439 lines
16 KiB
C
439 lines
16 KiB
C
/*
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* Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CONTEXT_H
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#define CONTEXT_H
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#if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31)
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#include <lib/el3_runtime/context_el2.h>
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#else
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/**
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* El1 context is required either when:
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* IMAGE_BL1 || ((!CTX_INCLUDE_EL2_REGS) && IMAGE_BL31)
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*/
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#include <lib/el3_runtime/context_el1.h>
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#endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */
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#include <lib/el3_runtime/cpu_data.h>
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#include <lib/el3_runtime/simd_ctx.h>
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#include <lib/utils_def.h>
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/*******************************************************************************
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* Constants that allow assembler code to access members of and the 'gp_regs'
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* structure at their correct offsets.
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******************************************************************************/
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#define CTX_GPREGS_OFFSET U(0x0)
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#define CTX_GPREG_X0 U(0x0)
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#define CTX_GPREG_X1 U(0x8)
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#define CTX_GPREG_X2 U(0x10)
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#define CTX_GPREG_X3 U(0x18)
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#define CTX_GPREG_X4 U(0x20)
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#define CTX_GPREG_X5 U(0x28)
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#define CTX_GPREG_X6 U(0x30)
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#define CTX_GPREG_X7 U(0x38)
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#define CTX_GPREG_X8 U(0x40)
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#define CTX_GPREG_X9 U(0x48)
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#define CTX_GPREG_X10 U(0x50)
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#define CTX_GPREG_X11 U(0x58)
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#define CTX_GPREG_X12 U(0x60)
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#define CTX_GPREG_X13 U(0x68)
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#define CTX_GPREG_X14 U(0x70)
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#define CTX_GPREG_X15 U(0x78)
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#define CTX_GPREG_X16 U(0x80)
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#define CTX_GPREG_X17 U(0x88)
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#define CTX_GPREG_X18 U(0x90)
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#define CTX_GPREG_X19 U(0x98)
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#define CTX_GPREG_X20 U(0xa0)
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#define CTX_GPREG_X21 U(0xa8)
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#define CTX_GPREG_X22 U(0xb0)
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#define CTX_GPREG_X23 U(0xb8)
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#define CTX_GPREG_X24 U(0xc0)
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#define CTX_GPREG_X25 U(0xc8)
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#define CTX_GPREG_X26 U(0xd0)
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#define CTX_GPREG_X27 U(0xd8)
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#define CTX_GPREG_X28 U(0xe0)
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#define CTX_GPREG_X29 U(0xe8)
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#define CTX_GPREG_LR U(0xf0)
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#define CTX_GPREG_SP_EL0 U(0xf8)
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#define CTX_GPREGS_END U(0x100)
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/*******************************************************************************
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* Constants that allow assembler code to access members of and the 'el3_state'
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* structure at their correct offsets. Note that some of the registers are only
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* 32-bits wide but are stored as 64-bit values for convenience
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******************************************************************************/
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#define CTX_EL3STATE_OFFSET (CTX_GPREGS_OFFSET + CTX_GPREGS_END)
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#define CTX_SCR_EL3 U(0x0)
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#define CTX_ESR_EL3 U(0x8)
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#define CTX_RUNTIME_SP U(0x10)
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#define CTX_SPSR_EL3 U(0x18)
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#define CTX_ELR_EL3 U(0x20)
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#define CTX_PMCR_EL0 U(0x28)
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#define CTX_IS_IN_EL3 U(0x30)
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#define CTX_MDCR_EL3 U(0x38)
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/* Constants required in supporting nested exception in EL3 */
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#define CTX_SAVED_ELR_EL3 U(0x40)
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/*
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* General purpose flag, to save various EL3 states
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* FFH mode : Used to identify if handling nested exception
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* KFH mode : Used as counter value
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*/
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#define CTX_NESTED_EA_FLAG U(0x48)
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#if FFH_SUPPORT
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#define CTX_SAVED_ESR_EL3 U(0x50)
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#define CTX_SAVED_SPSR_EL3 U(0x58)
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#define CTX_SAVED_GPREG_LR U(0x60)
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#define CTX_EL3STATE_END U(0x70) /* Align to the next 16 byte boundary */
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#else
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#define CTX_EL3STATE_END U(0x50) /* Align to the next 16 byte boundary */
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#endif /* FFH_SUPPORT */
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/*******************************************************************************
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* Registers related to CVE-2018-3639
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******************************************************************************/
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#define CTX_CVE_2018_3639_OFFSET (CTX_EL3STATE_OFFSET + CTX_EL3STATE_END)
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#define CTX_CVE_2018_3639_DISABLE U(0)
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#define CTX_CVE_2018_3639_END U(0x10) /* Align to the next 16 byte boundary */
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/*******************************************************************************
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* Registers related to ERRATA_SPECULATIVE_AT
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*
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* This is essential as with EL1 and EL2 context registers being decoupled,
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* both will not be present for a given build configuration.
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* As ERRATA_SPECULATIVE_AT errata requires SCTLR_EL1 and TCR_EL1 registers
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* independent of the above logic, we need explicit context entries to be
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* reserved for these registers.
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*
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* NOTE: Based on this we end up with following different configurations depending
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* on the presence of errata and inclusion of EL1 or EL2 context.
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*
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* ============================================================================
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* | ERRATA_SPECULATIVE_AT | EL1 context| Memory allocation(Sctlr_el1,Tcr_el1)|
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* ============================================================================
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* | 0 | 0 | None |
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* | 0 | 1 | EL1 C-Context structure |
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* | 1 | 0 | Errata Context Offset Entries |
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* | 1 | 1 | Errata Context Offset Entries |
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* ============================================================================
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*
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* In the above table, when ERRATA_SPECULATIVE_AT=1, EL1_Context=0, it implies
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* there is only EL2 context and memory for SCTLR_EL1 and TCR_EL1 registers is
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* reserved explicitly under ERRATA_SPECULATIVE_AT build flag here.
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*
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* In situations when EL1_Context=1 and ERRATA_SPECULATIVE_AT=1, since SCTLR_EL1
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* and TCR_EL1 registers will be modified under errata and it happens at the
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* early in the codeflow prior to el1 context (save and restore operations),
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* context memory still will be reserved under the errata logic here explicitly.
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* These registers will not be part of EL1 context save & restore routines.
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*
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* Only when ERRATA_SPECULATIVE_AT=0, EL1_Context=1, for this combination,
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* SCTLR_EL1 and TCR_EL1 will be part of EL1 context structure (context_el1.h)
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* -----------------------------------------------------------------------------
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******************************************************************************/
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#define CTX_ERRATA_SPEC_AT_OFFSET (CTX_CVE_2018_3639_OFFSET + CTX_CVE_2018_3639_END)
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#if ERRATA_SPECULATIVE_AT
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#define CTX_ERRATA_SPEC_AT_SCTLR_EL1 U(0x0)
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#define CTX_ERRATA_SPEC_AT_TCR_EL1 U(0x8)
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#define CTX_ERRATA_SPEC_AT_END U(0x10) /* Align to the next 16 byte boundary */
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#else
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#define CTX_ERRATA_SPEC_AT_END U(0x0)
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#endif /* ERRATA_SPECULATIVE_AT */
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/*******************************************************************************
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* Registers related to ARMv8.3-PAuth.
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******************************************************************************/
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#define CTX_PAUTH_REGS_OFFSET (CTX_ERRATA_SPEC_AT_OFFSET + CTX_ERRATA_SPEC_AT_END)
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#if CTX_INCLUDE_PAUTH_REGS
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#define CTX_PACIAKEY_LO U(0x0)
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#define CTX_PACIAKEY_HI U(0x8)
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#define CTX_PACIBKEY_LO U(0x10)
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#define CTX_PACIBKEY_HI U(0x18)
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#define CTX_PACDAKEY_LO U(0x20)
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#define CTX_PACDAKEY_HI U(0x28)
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#define CTX_PACDBKEY_LO U(0x30)
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#define CTX_PACDBKEY_HI U(0x38)
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#define CTX_PACGAKEY_LO U(0x40)
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#define CTX_PACGAKEY_HI U(0x48)
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#define CTX_PAUTH_REGS_END U(0x50) /* Align to the next 16 byte boundary */
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#else
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#define CTX_PAUTH_REGS_END U(0)
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#endif /* CTX_INCLUDE_PAUTH_REGS */
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/*******************************************************************************
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* Registers initialised in a per-world context.
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******************************************************************************/
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#define CTX_CPTR_EL3 U(0x0)
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#define CTX_MPAM3_EL3 U(0x8)
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#define CTX_PERWORLD_EL3STATE_END U(0x10)
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#ifndef __ASSEMBLER__
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#include <stdint.h>
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#include <lib/cassert.h>
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/*
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* Common constants to help define the 'cpu_context' structure and its
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* members below.
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*/
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#define DWORD_SHIFT U(3)
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#define DEFINE_REG_STRUCT(name, num_regs) \
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typedef struct name { \
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uint64_t ctx_regs[num_regs]; \
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} __aligned(16) name##_t
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/* Constants to determine the size of individual context structures */
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#define CTX_GPREG_ALL (CTX_GPREGS_END >> DWORD_SHIFT)
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#define CTX_EL3STATE_ALL (CTX_EL3STATE_END >> DWORD_SHIFT)
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#define CTX_CVE_2018_3639_ALL (CTX_CVE_2018_3639_END >> DWORD_SHIFT)
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#if ERRATA_SPECULATIVE_AT
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#define CTX_ERRATA_SPEC_AT_ALL (CTX_ERRATA_SPEC_AT_END >> DWORD_SHIFT)
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#endif
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#if CTX_INCLUDE_PAUTH_REGS
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# define CTX_PAUTH_REGS_ALL (CTX_PAUTH_REGS_END >> DWORD_SHIFT)
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#endif
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/*
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* AArch64 general purpose register context structure. Usually x0-x18,
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* lr are saved as the compiler is expected to preserve the remaining
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* callee saved registers if used by the C runtime and the assembler
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* does not touch the remaining. But in case of world switch during
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* exception handling, we need to save the callee registers too.
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*/
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DEFINE_REG_STRUCT(gp_regs, CTX_GPREG_ALL);
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/*
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* Miscellaneous registers used by EL3 firmware to maintain its state
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* across exception entries and exits
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*/
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DEFINE_REG_STRUCT(el3_state, CTX_EL3STATE_ALL);
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/* Function pointer used by CVE-2018-3639 dynamic mitigation */
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DEFINE_REG_STRUCT(cve_2018_3639, CTX_CVE_2018_3639_ALL);
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/* Registers associated to Errata_Speculative */
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#if ERRATA_SPECULATIVE_AT
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DEFINE_REG_STRUCT(errata_speculative_at, CTX_ERRATA_SPEC_AT_ALL);
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#endif
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/* Registers associated to ARMv8.3-PAuth */
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#if CTX_INCLUDE_PAUTH_REGS
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DEFINE_REG_STRUCT(pauth, CTX_PAUTH_REGS_ALL);
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#endif
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/*
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* Macros to access members of any of the above structures using their
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* offsets
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*/
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#define read_ctx_reg(ctx, offset) ((ctx)->ctx_regs[(offset) >> DWORD_SHIFT])
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#define write_ctx_reg(ctx, offset, val) (((ctx)->ctx_regs[(offset) >> DWORD_SHIFT]) \
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= (uint64_t) (val))
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/*
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* Top-level context structure which is used by EL3 firmware to preserve
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* the state of a core at the next lower EL in a given security state and
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* save enough EL3 meta data to be able to return to that EL and security
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* state. The context management library will be used to ensure that
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* SP_EL3 always points to an instance of this structure at exception
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* entry and exit.
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*/
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typedef struct cpu_context {
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gp_regs_t gpregs_ctx;
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el3_state_t el3state_ctx;
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cve_2018_3639_t cve_2018_3639_ctx;
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#if ERRATA_SPECULATIVE_AT
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errata_speculative_at_t errata_speculative_at_ctx;
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#endif
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#if CTX_INCLUDE_PAUTH_REGS
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pauth_t pauth_ctx;
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#endif
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#if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31)
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el2_sysregs_t el2_sysregs_ctx;
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#else
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/* El1 context should be included only either for IMAGE_BL1,
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* or for IMAGE_BL31 when CTX_INCLUDE_EL2_REGS=0:
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* When SPMD_SPM_AT_SEL2=1, SPMC at S-EL2 takes care of saving
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* and restoring EL1 registers. In this case, BL31 at EL3 can
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* exclude save and restore of EL1 context registers.
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*/
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el1_sysregs_t el1_sysregs_ctx;
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#endif
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} cpu_context_t;
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/*
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* Per-World Context.
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* It stores registers whose values can be shared across CPUs.
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*/
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typedef struct per_world_context {
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uint64_t ctx_cptr_el3;
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uint64_t ctx_mpam3_el3;
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} per_world_context_t;
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extern per_world_context_t per_world_context[CPU_DATA_CONTEXT_NUM];
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/* Macros to access members of the 'cpu_context_t' structure */
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#define get_el3state_ctx(h) (&((cpu_context_t *) h)->el3state_ctx)
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#if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31)
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#define get_el2_sysregs_ctx(h) (&((cpu_context_t *) h)->el2_sysregs_ctx)
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#else
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#define get_el1_sysregs_ctx(h) (&((cpu_context_t *) h)->el1_sysregs_ctx)
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#endif
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#define get_gpregs_ctx(h) (&((cpu_context_t *) h)->gpregs_ctx)
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#define get_cve_2018_3639_ctx(h) (&((cpu_context_t *) h)->cve_2018_3639_ctx)
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#if ERRATA_SPECULATIVE_AT
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#define get_errata_speculative_at_ctx(h) (&((cpu_context_t *) h)->errata_speculative_at_ctx)
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#endif
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#if CTX_INCLUDE_PAUTH_REGS
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# define get_pauth_ctx(h) (&((cpu_context_t *) h)->pauth_ctx)
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#endif
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/*
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* Compile time assertions related to the 'cpu_context' structure to
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* ensure that the assembler and the compiler view of the offsets of
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* the structure members is the same.
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*/
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CASSERT(CTX_GPREGS_OFFSET == __builtin_offsetof(cpu_context_t, gpregs_ctx),
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assert_core_context_gp_offset_mismatch);
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CASSERT(CTX_EL3STATE_OFFSET == __builtin_offsetof(cpu_context_t, el3state_ctx),
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assert_core_context_el3state_offset_mismatch);
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CASSERT(CTX_CVE_2018_3639_OFFSET == __builtin_offsetof(cpu_context_t, cve_2018_3639_ctx),
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assert_core_context_cve_2018_3639_offset_mismatch);
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#if ERRATA_SPECULATIVE_AT
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CASSERT(CTX_ERRATA_SPEC_AT_OFFSET == __builtin_offsetof(cpu_context_t, errata_speculative_at_ctx),
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assert_core_context_errata_speculative_at_offset_mismatch);
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#endif
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#if CTX_INCLUDE_PAUTH_REGS
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CASSERT(CTX_PAUTH_REGS_OFFSET == __builtin_offsetof(cpu_context_t, pauth_ctx),
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assert_core_context_pauth_offset_mismatch);
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#endif /* CTX_INCLUDE_PAUTH_REGS */
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/*
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* Helper macro to set the general purpose registers that correspond to
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* parameters in an aapcs_64 call i.e. x0-x7
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*/
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#define set_aapcs_args0(ctx, x0) do { \
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write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X0, x0); \
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} while (0)
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#define set_aapcs_args1(ctx, x0, x1) do { \
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write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X1, x1); \
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set_aapcs_args0(ctx, x0); \
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} while (0)
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#define set_aapcs_args2(ctx, x0, x1, x2) do { \
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write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X2, x2); \
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set_aapcs_args1(ctx, x0, x1); \
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} while (0)
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#define set_aapcs_args3(ctx, x0, x1, x2, x3) do { \
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write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X3, x3); \
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set_aapcs_args2(ctx, x0, x1, x2); \
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} while (0)
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#define set_aapcs_args4(ctx, x0, x1, x2, x3, x4) do { \
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write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X4, x4); \
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set_aapcs_args3(ctx, x0, x1, x2, x3); \
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} while (0)
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#define set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5) do { \
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write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X5, x5); \
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set_aapcs_args4(ctx, x0, x1, x2, x3, x4); \
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} while (0)
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#define set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6) do { \
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write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X6, x6); \
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set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5); \
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} while (0)
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#define set_aapcs_args7(ctx, x0, x1, x2, x3, x4, x5, x6, x7) do { \
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write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X7, x7); \
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set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6); \
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} while (0)
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/*******************************************************************************
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* Function prototypes
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******************************************************************************/
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#if CTX_INCLUDE_FPREGS
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void fpregs_context_save(simd_regs_t *regs);
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void fpregs_context_restore(simd_regs_t *regs);
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#endif
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/*******************************************************************************
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* The next four inline functions are required for IMAGE_BL1, as well as for
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* IMAGE_BL31 for the below combinations.
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* ============================================================================
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* | ERRATA_SPECULATIVE_AT| CTX_INCLUDE_EL2_REGS | Combination |
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* ============================================================================
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* | 0 | 0 | Valid (EL1 ctx) |
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* |______________________|______________________|____________________________|
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* | | | Invalid (No Errata/EL1 Ctx)|
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* | 0 | 1 | Hence commented out. |
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* |______________________|______________________|____________________________|
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* | | | |
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* | 1 | 0 | Valid (Errata ctx) |
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* |______________________|______________________|____________________________|
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* | | | |
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* | 1 | 1 | Valid (Errata ctx) |
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* |______________________|______________________|____________________________|
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* ============================================================================
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******************************************************************************/
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#if (IMAGE_BL1 || ((ERRATA_SPECULATIVE_AT) || (!CTX_INCLUDE_EL2_REGS)))
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static inline void write_ctx_sctlr_el1_reg_errata(cpu_context_t *ctx, u_register_t val)
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{
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#if (ERRATA_SPECULATIVE_AT)
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write_ctx_reg(get_errata_speculative_at_ctx(ctx),
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CTX_ERRATA_SPEC_AT_SCTLR_EL1, val);
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#else
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write_el1_ctx_common(get_el1_sysregs_ctx(ctx), sctlr_el1, val);
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#endif /* ERRATA_SPECULATIVE_AT */
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}
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static inline void write_ctx_tcr_el1_reg_errata(cpu_context_t *ctx, u_register_t val)
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{
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#if (ERRATA_SPECULATIVE_AT)
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write_ctx_reg(get_errata_speculative_at_ctx(ctx),
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CTX_ERRATA_SPEC_AT_TCR_EL1, val);
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#else
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write_el1_ctx_common(get_el1_sysregs_ctx(ctx), tcr_el1, val);
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#endif /* ERRATA_SPECULATIVE_AT */
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}
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static inline u_register_t read_ctx_sctlr_el1_reg_errata(cpu_context_t *ctx)
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{
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#if (ERRATA_SPECULATIVE_AT)
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return read_ctx_reg(get_errata_speculative_at_ctx(ctx),
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CTX_ERRATA_SPEC_AT_SCTLR_EL1);
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#else
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return read_el1_ctx_common(get_el1_sysregs_ctx(ctx), sctlr_el1);
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#endif /* ERRATA_SPECULATIVE_AT */
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}
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static inline u_register_t read_ctx_tcr_el1_reg_errata(cpu_context_t *ctx)
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{
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#if (ERRATA_SPECULATIVE_AT)
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return read_ctx_reg(get_errata_speculative_at_ctx(ctx),
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CTX_ERRATA_SPEC_AT_TCR_EL1);
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#else
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return read_el1_ctx_common(get_el1_sysregs_ctx(ctx), tcr_el1);
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#endif /* ERRATA_SPECULATIVE_AT */
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}
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#endif /* (IMAGE_BL1 || ((ERRATA_SPECULATIVE_AT) || (!CTX_INCLUDE_EL2_REGS))) */
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#endif /* __ASSEMBLER__ */
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#endif /* CONTEXT_H */
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