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c3cf06f1a3
All identifiers, regardless of use, that start with two underscores are reserved. This means they can't be used in header guards. The style that this project is now to use the full name of the file in capital letters followed by 'H'. For example, for a file called "uart_example.h", the header guard is UART_EXAMPLE_H. The exceptions are files that are imported from other projects: - CryptoCell driver - dt-bindings folders - zlib headers Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
258 lines
9.1 KiB
C
258 lines
9.1 KiB
C
/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#ifndef PHY_COMPHY_3700_H
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#define PHY_COMPHY_3700_H
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#define PLL_SET_DELAY_US 600
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#define COMPHY_PLL_TIMEOUT 1000
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#define REG_16_BIT_MASK 0xFFFF
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#define COMPHY_SELECTOR_PHY_REG 0xFC
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/* bit0: 0: Lane0 is GBE0; 1: Lane1 is PCIE */
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#define COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT BIT(0)
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/* bit4: 0: Lane1 is GBE1; 1: Lane1 is USB3 */
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#define COMPHY_SELECTOR_USB3_GBE1_SEL_BIT BIT(4)
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/* bit8: 0: Lane1 is USB, Lane2 is SATA; 1: Lane2 is USB3 */
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#define COMPHY_SELECTOR_USB3_PHY_SEL_BIT BIT(8)
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/* SATA PHY register offset */
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#define SATAPHY_LANE2_REG_BASE_OFFSET 0x200
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/* USB3 PHY offset compared to SATA PHY */
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#define USB3PHY_LANE2_REG_BASE_OFFSET 0x200
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/* Comphy lane2 indirect access register offset */
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#define COMPHY_LANE2_INDIR_ADDR_OFFSET 0x0
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#define COMPHY_LANE2_INDIR_DATA_OFFSET 0x4
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/* PHY shift to get related register address */
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enum {
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PCIE = 1,
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USB3,
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};
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#define PCIEPHY_SHFT 2
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#define USB3PHY_SHFT 2
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#define PHY_SHFT(unit) ((unit == PCIE) ? PCIEPHY_SHFT : USB3PHY_SHFT)
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/* PHY register */
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#define COMPHY_POWER_PLL_CTRL 0x01
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#define PWR_PLL_CTRL_ADDR(unit) (COMPHY_POWER_PLL_CTRL * PHY_SHFT(unit))
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#define PU_IVREF_BIT BIT(15)
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#define PU_PLL_BIT BIT(14)
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#define PU_RX_BIT BIT(13)
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#define PU_TX_BIT BIT(12)
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#define PU_TX_INTP_BIT BIT(11)
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#define PU_DFE_BIT BIT(10)
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#define RESET_DTL_RX_BIT BIT(9)
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#define PLL_LOCK_BIT BIT(8)
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#define REF_FREF_SEL_OFFSET 0
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#define REF_FREF_SEL_MASK (0x1F << REF_FREF_SEL_OFFSET)
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#define REF_CLOCK_SPEED_25M (0x1 << REF_FREF_SEL_OFFSET)
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#define REF_CLOCK_SPEED_30M (0x2 << REF_FREF_SEL_OFFSET)
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#define PCIE_REF_CLOCK_SPEED_25M REF_CLOCK_SPEED_30M
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#define USB3_REF_CLOCK_SPEED_25M REF_CLOCK_SPEED_30M
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#define REF_CLOCK_SPEED_40M (0x3 << REF_FREF_SEL_OFFSET)
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#define REF_CLOCK_SPEED_50M (0x4 << REF_FREF_SEL_OFFSET)
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#define PHY_MODE_OFFSET 5
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#define PHY_MODE_MASK (7 << PHY_MODE_OFFSET)
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#define PHY_MODE_SATA (0x0 << PHY_MODE_OFFSET)
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#define PHY_MODE_PCIE (0x3 << PHY_MODE_OFFSET)
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#define PHY_MODE_SGMII (0x4 << PHY_MODE_OFFSET)
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#define PHY_MODE_USB3 (0x5 << PHY_MODE_OFFSET)
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#define COMPHY_KVCO_CAL_CTRL 0x02
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#define KVCO_CAL_CTRL_ADDR(unit) (COMPHY_KVCO_CAL_CTRL * PHY_SHFT(unit))
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#define USE_MAX_PLL_RATE_BIT BIT(12)
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#define SPEED_PLL_OFFSET 2
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#define SPEED_PLL_MASK (0x3F << SPEED_PLL_OFFSET)
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#define SPEED_PLL_VALUE_16 (0x10 << SPEED_PLL_OFFSET)
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#define COMPHY_RESERVED_REG 0x0E
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#define PHYCTRL_FRM_PIN_BIT BIT(13)
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#define COMPHY_LOOPBACK_REG0 0x23
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#define DIG_LB_EN_ADDR(unit) (COMPHY_LOOPBACK_REG0 * PHY_SHFT(unit))
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#define SEL_DATA_WIDTH_OFFSET 10
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#define SEL_DATA_WIDTH_MASK (0x3 << SEL_DATA_WIDTH_OFFSET)
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#define DATA_WIDTH_10BIT (0x0 << SEL_DATA_WIDTH_OFFSET)
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#define DATA_WIDTH_20BIT (0x1 << SEL_DATA_WIDTH_OFFSET)
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#define DATA_WIDTH_40BIT (0x2 << SEL_DATA_WIDTH_OFFSET)
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#define PLL_READY_TX_BIT BIT(4)
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#define COMPHY_SYNC_PATTERN_REG 0x24
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#define SYNC_PATTERN_REG_ADDR(unit) (COMPHY_SYNC_PATTERN_REG * \
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PHY_SHFT(unit))
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#define TXD_INVERT_BIT BIT(10)
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#define RXD_INVERT_BIT BIT(11)
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#define COMPHY_SYNC_MASK_GEN_REG 0x25
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#define PHY_GEN_MAX_OFFSET 10
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#define PHY_GEN_MAX_MASK (3 << PHY_GEN_MAX_OFFSET)
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#define PHY_GEN_USB3_5G (1 << PHY_GEN_MAX_OFFSET)
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#define COMPHY_ISOLATION_CTRL_REG 0x26
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#define ISOLATION_CTRL_REG_ADDR(unit) (COMPHY_ISOLATION_CTRL_REG * \
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PHY_SHFT(unit))
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#define PHY_ISOLATE_MODE BIT(15)
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#define COMPHY_MISC_REG0_ADDR 0x4F
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#define MISC_REG0_ADDR(unit) (COMPHY_MISC_REG0_ADDR * PHY_SHFT(unit))
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#define CLK100M_125M_EN BIT(4)
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#define CLK500M_EN BIT(7)
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#define PHY_REF_CLK_SEL BIT(10)
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#define MISC_REG0_DEFAULT_VALUE 0xA00D
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#define COMPHY_REG_GEN2_SET_2 0x3e
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#define GEN2_SETTING_2_ADDR(unit) (COMPHY_REG_GEN2_SET_2 * PHY_SHFT(unit))
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#define G2_TX_SSC_AMP_VALUE_20 BIT(14)
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#define G2_TX_SSC_AMP_OFF 9
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#define G2_TX_SSC_AMP_LEN 7
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#define G2_TX_SSC_AMP_MASK (((1 << G2_TX_SSC_AMP_LEN) - 1) << \
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G2_TX_SSC_AMP_OFF)
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#define COMPHY_REG_GEN2_SET_3 0x3f
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#define GEN2_SETTING_3_ADDR(unit) (COMPHY_REG_GEN2_SET_3 * PHY_SHFT(unit))
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#define G3_TX_SSC_AMP_OFF 9
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#define G3_TX_SSC_AMP_LEN 7
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#define G3_TX_SSC_AMP_MASK (((1 << G2_TX_SSC_AMP_LEN) - 1) << \
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G2_TX_SSC_AMP_OFF)
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#define G3_VREG_RXTX_MAS_ISET_OFF 7
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#define G3_VREG_RXTX_MAS_ISET_60U (0 << G3_VREG_RXTX_MAS_ISET_OFF)
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#define G3_VREG_RXTX_MAS_ISET_80U (1 << G3_VREG_RXTX_MAS_ISET_OFF)
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#define G3_VREG_RXTX_MAS_ISET_100U (2 << G3_VREG_RXTX_MAS_ISET_OFF)
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#define G3_VREG_RXTX_MAS_ISET_120U (3 << G3_VREG_RXTX_MAS_ISET_OFF)
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#define G3_VREG_RXTX_MAS_ISET_MASK (BIT(7) | BIT(8))
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#define RSVD_PH03FH_6_0_OFF 0
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#define RSVD_PH03FH_6_0_LEN 7
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#define RSVD_PH03FH_6_0_MASK (((1 << RSVD_PH03FH_6_0_LEN) - 1) << \
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RSVD_PH03FH_6_0_OFF)
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#define COMPHY_REG_UNIT_CTRL_ADDR 0x48
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#define UNIT_CTRL_ADDR(unit) (COMPHY_REG_UNIT_CTRL_ADDR * \
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PHY_SHFT(unit))
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#define IDLE_SYNC_EN BIT(12)
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#define UNIT_CTRL_DEFAULT_VALUE 0x60
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#define COMPHY_MISC_REG1_ADDR 0x73
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#define MISC_REG1_ADDR(unit) (COMPHY_MISC_REG1_ADDR * PHY_SHFT(unit))
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#define SEL_BITS_PCIE_FORCE BIT(15)
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#define COMPHY_REG_GEN3_SETTINGS_3 0x112
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#define COMPHY_GEN_FFE_CAP_SEL_MASK 0xF
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#define COMPHY_GEN_FFE_CAP_SEL_VALUE 0xF
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#define COMPHY_REG_LANE_CFG0_ADDR 0x180
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#define LANE_CFG0_ADDR(unit) (COMPHY_REG_LANE_CFG0_ADDR * \
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PHY_SHFT(unit))
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#define PRD_TXDEEMPH0_MASK BIT(0)
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#define PRD_TXMARGIN_MASK (BIT(1) | BIT(2) | BIT(3))
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#define PRD_TXSWING_MASK BIT(4)
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#define CFG_TX_ALIGN_POS_MASK (BIT(5) | BIT(6) | BIT(7) | BIT(8))
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#define COMPHY_REG_LANE_CFG1_ADDR 0x181
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#define LANE_CFG1_ADDR(unit) (COMPHY_REG_LANE_CFG1_ADDR * \
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PHY_SHFT(unit))
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#define PRD_TXDEEMPH1_MASK BIT(15)
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#define USE_MAX_PLL_RATE_EN BIT(9)
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#define TX_DET_RX_MODE BIT(6)
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#define GEN2_TX_DATA_DLY_MASK (BIT(3) | BIT(4))
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#define GEN2_TX_DATA_DLY_DEFT (2 << 3)
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#define TX_ELEC_IDLE_MODE_EN BIT(0)
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#define COMPHY_REG_LANE_STATUS1_ADDR 0x183
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#define LANE_STATUS1_ADDR(unit) (COMPHY_REG_LANE_STATUS1_ADDR * \
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PHY_SHFT(unit))
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#define TXDCLK_PCLK_EN BIT(0)
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#define COMPHY_REG_LANE_CFG4_ADDR 0x188
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#define LANE_CFG4_ADDR(unit) (COMPHY_REG_LANE_CFG4_ADDR * \
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PHY_SHFT(unit))
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#define SPREAD_SPECTRUM_CLK_EN BIT(7)
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#define COMPHY_REG_GLOB_PHY_CTRL0_ADDR 0x1C1
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#define GLOB_PHY_CTRL0_ADDR(unit) (COMPHY_REG_GLOB_PHY_CTRL0_ADDR * \
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PHY_SHFT(unit))
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#define SOFT_RESET BIT(0)
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#define MODE_REFDIV 0x30
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#define MODE_CORE_CLK_FREQ_SEL BIT(9)
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#define MODE_PIPE_WIDTH_32 BIT(3)
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#define MODE_REFDIV_OFFSET 4
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#define MODE_REFDIV_LEN 2
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#define MODE_REFDIV_MASK (0x3 << MODE_REFDIV_OFFSET)
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#define MODE_REFDIV_BY_4 (0x2 << MODE_REFDIV_OFFSET)
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#define COMPHY_REG_TEST_MODE_CTRL_ADDR 0x1C2
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#define TEST_MODE_CTRL_ADDR(unit) (COMPHY_REG_TEST_MODE_CTRL_ADDR * \
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PHY_SHFT(unit))
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#define MODE_MARGIN_OVERRIDE BIT(2)
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#define COMPHY_REG_GLOB_CLK_SRC_LO_ADDR 0x1C3
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#define GLOB_CLK_SRC_LO_ADDR(unit) (COMPHY_REG_GLOB_CLK_SRC_LO_ADDR * \
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PHY_SHFT(unit))
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#define MODE_CLK_SRC BIT(0)
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#define BUNDLE_PERIOD_SEL BIT(1)
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#define BUNDLE_PERIOD_SCALE (BIT(2) | BIT(3))
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#define BUNDLE_SAMPLE_CTRL BIT(4)
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#define PLL_READY_DLY (BIT(5) | BIT(6) | BIT(7))
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#define CFG_SEL_20B BIT(15)
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#define COMPHY_REG_PWR_MGM_TIM1_ADDR 0x1D0
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#define PWR_MGM_TIM1_ADDR(unit) (COMPHY_REG_PWR_MGM_TIM1_ADDR * \
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PHY_SHFT(unit))
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#define CFG_PM_OSCCLK_WAIT_OFF 12
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#define CFG_PM_OSCCLK_WAIT_LEN 4
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#define CFG_PM_OSCCLK_WAIT_MASK (((1 << CFG_PM_OSCCLK_WAIT_LEN) - 1) \
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<< CFG_PM_OSCCLK_WAIT_OFF)
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#define CFG_PM_RXDEN_WAIT_OFF 8
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#define CFG_PM_RXDEN_WAIT_LEN 4
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#define CFG_PM_RXDEN_WAIT_MASK (((1 << CFG_PM_RXDEN_WAIT_LEN) - 1) \
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<< CFG_PM_RXDEN_WAIT_OFF)
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#define CFG_PM_RXDEN_WAIT_1_UNIT (1 << CFG_PM_RXDEN_WAIT_OFF)
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#define CFG_PM_RXDLOZ_WAIT_OFF 0
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#define CFG_PM_RXDLOZ_WAIT_LEN 8
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#define CFG_PM_RXDLOZ_WAIT_MASK (((1 << CFG_PM_RXDLOZ_WAIT_LEN) - 1) \
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<< CFG_PM_RXDLOZ_WAIT_OFF)
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#define CFG_PM_RXDLOZ_WAIT_7_UNIT (7 << CFG_PM_RXDLOZ_WAIT_OFF)
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#define CFG_PM_RXDLOZ_WAIT_12_UNIT (0xC << CFG_PM_RXDLOZ_WAIT_OFF)
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/* SGMII */
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#define COMPHY_PHY_CFG1_OFFSET(lane) ((1 - (lane)) * 0x28)
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#define PIN_PU_IVEREF_BIT BIT(1)
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#define PIN_RESET_CORE_BIT BIT(11)
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#define PIN_RESET_COMPHY_BIT BIT(12)
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#define PIN_PU_PLL_BIT BIT(16)
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#define PIN_PU_RX_BIT BIT(17)
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#define PIN_PU_TX_BIT BIT(18)
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#define PIN_TX_IDLE_BIT BIT(19)
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#define GEN_RX_SEL_OFFSET 22
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#define GEN_RX_SEL_MASK (0xF << GEN_RX_SEL_OFFSET)
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#define GEN_TX_SEL_OFFSET 26
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#define GEN_TX_SEL_MASK (0xF << GEN_TX_SEL_OFFSET)
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#define PHY_RX_INIT_BIT BIT(30)
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#define SD_SPEED_1_25_G 0x6
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#define SD_SPEED_2_5_G 0x8
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/* COMPHY status reg:
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* lane0: PCIe/GbE0 PHY Status 1
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* lane1: USB3/GbE1 PHY Status 1
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*/
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#define COMPHY_PHY_STATUS_OFFSET(lane) (0x18 + (1 - (lane)) * 0x28)
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#define PHY_RX_INIT_DONE_BIT BIT(0)
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#define PHY_PLL_READY_RX_BIT BIT(2)
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#define PHY_PLL_READY_TX_BIT BIT(3)
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#define SGMIIPHY_ADDR(off, base) ((((off) & 0x00007FF) * 2) + (base))
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#define MAX_LANE_NR 3
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/* comphy API */
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int mvebu_3700_comphy_is_pll_locked(uint8_t comphy_index, uint32_t comphy_mode);
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int mvebu_3700_comphy_power_off(uint8_t comphy_index, uint32_t comphy_mode);
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int mvebu_3700_comphy_power_on(uint8_t comphy_index, uint32_t comphy_mode);
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#endif /* PHY_COMPHY_3700_H */
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