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0767d50e69
Add some AMU helper functions to allow configuring, reading and writing of the Group 0 and Group 1 counters. Documentation for these helpers will come in a separate patch. Change-Id: I656e070d2dae830c22414f694aa655341d4e2c40 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
110 lines
2.4 KiB
C
110 lines
2.4 KiB
C
/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <amu.h>
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#include <amu_private.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <assert.h>
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#include <debug.h>
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#define AMU_GROUP0_NR_COUNTERS 4
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int amu_supported(void)
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{
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uint64_t features;
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features = read_id_aa64pfr0_el1() >> ID_AA64PFR0_AMU_SHIFT;
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return (features & ID_AA64PFR0_AMU_MASK) == 1;
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}
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/*
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* Enable counters. This function is meant to be invoked
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* by the context management library before exiting from EL3.
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*/
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void amu_enable(int el2_unused)
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{
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uint64_t v;
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if (!amu_supported()) {
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WARN("Cannot enable AMU - not supported\n");
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return;
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}
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if (el2_unused) {
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/*
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* CPTR_EL2.TAM: Set to zero so any accesses to
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* the Activity Monitor registers do not trap to EL2.
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*/
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v = read_cptr_el2();
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v &= ~CPTR_EL2_TAM_BIT;
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write_cptr_el2(v);
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}
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/*
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* CPTR_EL3.TAM: Set to zero so that any accesses to
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* the Activity Monitor registers do not trap to EL3.
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*/
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v = read_cptr_el3();
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v &= ~TAM_BIT;
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write_cptr_el3(v);
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/* Enable group 0 counters */
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write_amcntenset0_el0(AMU_GROUP0_COUNTERS_MASK);
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/* Enable group 1 counters */
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write_amcntenset1_el0(AMU_GROUP1_COUNTERS_MASK);
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}
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/* Read the group 0 counter identified by the given `idx`. */
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uint64_t amu_group0_cnt_read(int idx)
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{
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assert(amu_supported());
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assert(idx >= 0 && idx < AMU_GROUP0_NR_COUNTERS);
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return amu_group0_cnt_read_internal(idx);
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}
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/* Write the group 0 counter identified by the given `idx` with `val`. */
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void amu_group0_cnt_write(int idx, uint64_t val)
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{
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assert(amu_supported());
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assert(idx >= 0 && idx < AMU_GROUP0_NR_COUNTERS);
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amu_group0_cnt_write_internal(idx, val);
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isb();
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}
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/* Read the group 1 counter identified by the given `idx`. */
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uint64_t amu_group1_cnt_read(int idx)
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{
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assert(amu_supported());
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assert(idx >= 0 && idx < AMU_GROUP1_NR_COUNTERS);
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return amu_group1_cnt_read_internal(idx);
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}
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/* Write the group 1 counter identified by the given `idx` with `val`. */
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void amu_group1_cnt_write(int idx, uint64_t val)
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{
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assert(amu_supported());
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assert(idx >= 0 && idx < AMU_GROUP1_NR_COUNTERS);
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amu_group1_cnt_write_internal(idx, val);
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isb();
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}
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/*
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* Program the event type register for the given `idx` with
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* the event number `val`.
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*/
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void amu_group1_set_evtype(int idx, unsigned int val)
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{
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assert(amu_supported());
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assert (idx >= 0 && idx < AMU_GROUP1_NR_COUNTERS);
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amu_group1_set_evtype_internal(idx, val);
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isb();
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}
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