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https://github.com/ARM-software/arm-trusted-firmware.git
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29332bcd68
Add required code to support FCONF on STM32MP1 platform. The new FW_CONFIG DT file will be inside the FIP, and loaded by BL2. It will be used to configure the addresses where to load other binaries. BL2 should be agnostic of which BL32 is in the FIP (OP-TEE or SP_min), so optee_utils.c is always compiled, and some OP-TEE flags are removed. Change-Id: Id957b49b0117864136250bfc416664f815043ada Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
73 lines
2.2 KiB
C
73 lines
2.2 KiB
C
/*
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* Copyright (C) 2021, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef STM32MP1_STM32IMAGE_DEF_H
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#define STM32MP1_STM32IMAGE_DEF_H
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#ifdef AARCH32_SP_OPTEE
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#define STM32MP_DDR_S_SIZE U(0x01E00000) /* 30 MB */
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#define STM32MP_DDR_SHMEM_SIZE U(0x00200000) /* 2 MB */
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#else
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#define STM32MP_DDR_S_SIZE U(0)
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#define STM32MP_DDR_SHMEM_SIZE U(0)
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#endif
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#define STM32MP_BL2_SIZE U(0x0001C000) /* 112 KB for BL2 */
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#define STM32MP_DTB_SIZE U(0x00006000) /* 24 KB for DTB */
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#ifdef AARCH32_SP_OPTEE
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#define STM32MP_BL32_BASE STM32MP_SEC_SYSRAM_BASE
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#define STM32MP_BL2_BASE (STM32MP_SEC_SYSRAM_BASE + \
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STM32MP_SEC_SYSRAM_SIZE - \
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STM32MP_BL2_SIZE)
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/* OP-TEE loads from SYSRAM base to BL2 DTB start address */
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#define STM32MP_OPTEE_BASE STM32MP_BL32_BASE
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#define STM32MP_OPTEE_SIZE (STM32MP_SEC_SYSRAM_SIZE - \
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STM32MP_BL2_SIZE - STM32MP_DTB_SIZE)
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#define STM32MP_BL32_SIZE STM32MP_OPTEE_SIZE
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#else /* AARCH32_SP_OPTEE */
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#define STM32MP_BL32_SIZE U(0x00019000) /* 96 KB for BL32 */
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#define STM32MP_BL32_BASE (STM32MP_SEC_SYSRAM_BASE + \
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STM32MP_SEC_SYSRAM_SIZE - \
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STM32MP_BL32_SIZE)
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#define STM32MP_BL2_BASE (STM32MP_BL32_BASE - \
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STM32MP_BL2_SIZE)
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#endif /* AARCH32_SP_OPTEE */
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/* DTB initialization value */
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#define STM32MP_DTB_BASE (STM32MP_BL2_BASE - \
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STM32MP_DTB_SIZE)
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/*
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* MAX_MMAP_REGIONS is usually:
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* BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup
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*/
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#if defined(IMAGE_BL32)
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#define MAX_MMAP_REGIONS 6
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#endif
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/*******************************************************************************
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* STM32MP1 RAW partition offset for MTD devices
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******************************************************************************/
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#define STM32MP_NOR_BL33_OFFSET U(0x00080000)
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#ifdef AARCH32_SP_OPTEE
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#define STM32MP_NOR_TEEH_OFFSET U(0x00280000)
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#define STM32MP_NOR_TEED_OFFSET U(0x002C0000)
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#define STM32MP_NOR_TEEX_OFFSET U(0x00300000)
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#endif
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#define STM32MP_NAND_BL33_OFFSET U(0x00200000)
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#ifdef AARCH32_SP_OPTEE
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#define STM32MP_NAND_TEEH_OFFSET U(0x00600000)
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#define STM32MP_NAND_TEED_OFFSET U(0x00680000)
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#define STM32MP_NAND_TEEX_OFFSET U(0x00700000)
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#endif
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#endif /* STM32MP1_STM32IMAGE_DEF_H */
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