mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-16 01:24:27 +00:00

Rename driver file to BSEC2. Split header file in IP and feature parts. Add functions to access BSEC scratch register. Several corrections and improvements. Probe the driver earlier, especially to check debug features. Change-Id: I1981536398d598d67a19d2d7766dacc18de72ec1 Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com>
612 lines
12 KiB
C
612 lines
12 KiB
C
/*
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* Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <drivers/clk.h>
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#include <drivers/st/stm32_gpio.h>
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#include <drivers/st/stm32_iwdg.h>
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#include <lib/mmio.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <libfdt.h>
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#include <plat/common/platform.h>
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#include <platform_def.h>
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/* Internal layout of the 32bit OTP word board_id */
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#define BOARD_ID_BOARD_NB_MASK GENMASK(31, 16)
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#define BOARD_ID_BOARD_NB_SHIFT 16
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#define BOARD_ID_VARCPN_MASK GENMASK(15, 12)
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#define BOARD_ID_VARCPN_SHIFT 12
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#define BOARD_ID_REVISION_MASK GENMASK(11, 8)
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#define BOARD_ID_REVISION_SHIFT 8
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#define BOARD_ID_VARFG_MASK GENMASK(7, 4)
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#define BOARD_ID_VARFG_SHIFT 4
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#define BOARD_ID_BOM_MASK GENMASK(3, 0)
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#define BOARD_ID2NB(_id) (((_id) & BOARD_ID_BOARD_NB_MASK) >> \
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BOARD_ID_BOARD_NB_SHIFT)
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#define BOARD_ID2VARCPN(_id) (((_id) & BOARD_ID_VARCPN_MASK) >> \
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BOARD_ID_VARCPN_SHIFT)
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#define BOARD_ID2REV(_id) (((_id) & BOARD_ID_REVISION_MASK) >> \
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BOARD_ID_REVISION_SHIFT)
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#define BOARD_ID2VARFG(_id) (((_id) & BOARD_ID_VARFG_MASK) >> \
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BOARD_ID_VARFG_SHIFT)
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#define BOARD_ID2BOM(_id) ((_id) & BOARD_ID_BOM_MASK)
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#define TAMP_BOOT_MODE_BACKUP_REG_ID U(20)
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#define TAMP_BOOT_MODE_ITF_MASK U(0x0000FF00)
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#define TAMP_BOOT_MODE_ITF_SHIFT 8
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#define TAMP_BOOT_COUNTER_REG_ID U(21)
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#if defined(IMAGE_BL2)
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#define MAP_SEC_SYSRAM MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \
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STM32MP_SYSRAM_SIZE, \
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MT_MEMORY | \
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MT_RW | \
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MT_SECURE | \
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MT_EXECUTE_NEVER)
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#elif defined(IMAGE_BL32)
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#define MAP_SEC_SYSRAM MAP_REGION_FLAT(STM32MP_SEC_SYSRAM_BASE, \
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STM32MP_SEC_SYSRAM_SIZE, \
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MT_MEMORY | \
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MT_RW | \
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MT_SECURE | \
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MT_EXECUTE_NEVER)
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/* Non-secure SYSRAM is used a uncached memory for SCMI message transfer */
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#define MAP_NS_SYSRAM MAP_REGION_FLAT(STM32MP_NS_SYSRAM_BASE, \
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STM32MP_NS_SYSRAM_SIZE, \
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MT_DEVICE | \
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MT_RW | \
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MT_NS | \
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MT_EXECUTE_NEVER)
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#endif
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#define MAP_DEVICE1 MAP_REGION_FLAT(STM32MP1_DEVICE1_BASE, \
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STM32MP1_DEVICE1_SIZE, \
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MT_DEVICE | \
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MT_RW | \
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MT_SECURE | \
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MT_EXECUTE_NEVER)
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#define MAP_DEVICE2 MAP_REGION_FLAT(STM32MP1_DEVICE2_BASE, \
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STM32MP1_DEVICE2_SIZE, \
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MT_DEVICE | \
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MT_RW | \
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MT_SECURE | \
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MT_EXECUTE_NEVER)
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#if defined(IMAGE_BL2)
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static const mmap_region_t stm32mp1_mmap[] = {
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MAP_SEC_SYSRAM,
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MAP_DEVICE1,
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#if STM32MP_RAW_NAND
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MAP_DEVICE2,
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#endif
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{0}
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};
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#endif
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#if defined(IMAGE_BL32)
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static const mmap_region_t stm32mp1_mmap[] = {
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MAP_SEC_SYSRAM,
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MAP_NS_SYSRAM,
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MAP_DEVICE1,
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MAP_DEVICE2,
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{0}
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};
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#endif
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void configure_mmu(void)
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{
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mmap_add(stm32mp1_mmap);
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init_xlat_tables();
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enable_mmu_svc_mon(0);
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}
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uintptr_t stm32_get_gpio_bank_base(unsigned int bank)
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{
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if (bank == GPIO_BANK_Z) {
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return GPIOZ_BASE;
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}
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assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K);
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return GPIOA_BASE + (bank * GPIO_BANK_OFFSET);
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}
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uint32_t stm32_get_gpio_bank_offset(unsigned int bank)
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{
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if (bank == GPIO_BANK_Z) {
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return 0;
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}
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assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K);
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return bank * GPIO_BANK_OFFSET;
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}
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bool stm32_gpio_is_secure_at_reset(unsigned int bank)
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{
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if (bank == GPIO_BANK_Z) {
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return true;
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}
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return false;
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}
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unsigned long stm32_get_gpio_bank_clock(unsigned int bank)
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{
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if (bank == GPIO_BANK_Z) {
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return GPIOZ;
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}
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assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K);
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return GPIOA + (bank - GPIO_BANK_A);
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}
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int stm32_get_gpio_bank_pinctrl_node(void *fdt, unsigned int bank)
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{
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switch (bank) {
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case GPIO_BANK_A:
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case GPIO_BANK_B:
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case GPIO_BANK_C:
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case GPIO_BANK_D:
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case GPIO_BANK_E:
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case GPIO_BANK_F:
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case GPIO_BANK_G:
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case GPIO_BANK_H:
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case GPIO_BANK_I:
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case GPIO_BANK_J:
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case GPIO_BANK_K:
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return fdt_path_offset(fdt, "/soc/pin-controller");
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case GPIO_BANK_Z:
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return fdt_path_offset(fdt, "/soc/pin-controller-z");
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default:
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panic();
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}
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}
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#if STM32MP_UART_PROGRAMMER || !defined(IMAGE_BL2)
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/*
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* UART Management
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*/
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static const uintptr_t stm32mp1_uart_addresses[8] = {
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USART1_BASE,
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USART2_BASE,
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USART3_BASE,
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UART4_BASE,
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UART5_BASE,
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USART6_BASE,
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UART7_BASE,
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UART8_BASE,
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};
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uintptr_t get_uart_address(uint32_t instance_nb)
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{
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if ((instance_nb == 0U) ||
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(instance_nb > ARRAY_SIZE(stm32mp1_uart_addresses))) {
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return 0U;
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}
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return stm32mp1_uart_addresses[instance_nb - 1U];
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}
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#endif
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#if STM32MP_USB_PROGRAMMER
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struct gpio_bank_pin_list {
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uint32_t bank;
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uint32_t pin;
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};
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static const struct gpio_bank_pin_list gpio_list[] = {
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{ /* USART2_RX: GPIOA3 */
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.bank = 0U,
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.pin = 3U,
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},
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{ /* USART3_RX: GPIOB12 */
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.bank = 1U,
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.pin = 12U,
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},
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{ /* UART4_RX: GPIOB2 */
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.bank = 1U,
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.pin = 2U,
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},
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{ /* UART5_RX: GPIOB4 */
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.bank = 1U,
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.pin = 5U,
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},
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{ /* USART6_RX: GPIOC7 */
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.bank = 2U,
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.pin = 7U,
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},
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{ /* UART7_RX: GPIOF6 */
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.bank = 5U,
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.pin = 6U,
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},
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{ /* UART8_RX: GPIOE0 */
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.bank = 4U,
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.pin = 0U,
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},
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};
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void stm32mp1_deconfigure_uart_pins(void)
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{
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size_t i;
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for (i = 0U; i < ARRAY_SIZE(gpio_list); i++) {
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set_gpio_reset_cfg(gpio_list[i].bank, gpio_list[i].pin);
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}
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}
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#endif
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uint32_t stm32mp_get_chip_version(void)
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{
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uint32_t version = 0U;
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if (stm32mp1_dbgmcu_get_chip_version(&version) < 0) {
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INFO("Cannot get CPU version, debug disabled\n");
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return 0U;
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}
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return version;
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}
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uint32_t stm32mp_get_chip_dev_id(void)
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{
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uint32_t dev_id;
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if (stm32mp1_dbgmcu_get_chip_dev_id(&dev_id) < 0) {
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INFO("Use default chip ID, debug disabled\n");
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dev_id = STM32MP1_CHIP_ID;
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}
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return dev_id;
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}
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static uint32_t get_part_number(void)
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{
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static uint32_t part_number;
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if (part_number != 0U) {
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return part_number;
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}
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if (bsec_shadow_read_otp(&part_number, PART_NUMBER_OTP) != BSEC_OK) {
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panic();
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}
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part_number = (part_number & PART_NUMBER_OTP_PART_MASK) >>
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PART_NUMBER_OTP_PART_SHIFT;
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part_number |= stm32mp_get_chip_dev_id() << 16;
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return part_number;
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}
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static uint32_t get_cpu_package(void)
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{
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uint32_t package;
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if (bsec_shadow_read_otp(&package, PACKAGE_OTP) != BSEC_OK) {
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panic();
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}
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package = (package & PACKAGE_OTP_PKG_MASK) >>
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PACKAGE_OTP_PKG_SHIFT;
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return package;
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}
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void stm32mp_get_soc_name(char name[STM32_SOC_NAME_SIZE])
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{
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char *cpu_s, *cpu_r, *pkg;
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/* MPUs Part Numbers */
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switch (get_part_number()) {
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case STM32MP157C_PART_NB:
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cpu_s = "157C";
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break;
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case STM32MP157A_PART_NB:
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cpu_s = "157A";
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break;
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case STM32MP153C_PART_NB:
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cpu_s = "153C";
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break;
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case STM32MP153A_PART_NB:
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cpu_s = "153A";
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break;
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case STM32MP151C_PART_NB:
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cpu_s = "151C";
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break;
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case STM32MP151A_PART_NB:
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cpu_s = "151A";
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break;
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case STM32MP157F_PART_NB:
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cpu_s = "157F";
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break;
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case STM32MP157D_PART_NB:
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cpu_s = "157D";
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break;
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case STM32MP153F_PART_NB:
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cpu_s = "153F";
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break;
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case STM32MP153D_PART_NB:
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cpu_s = "153D";
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break;
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case STM32MP151F_PART_NB:
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cpu_s = "151F";
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break;
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case STM32MP151D_PART_NB:
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cpu_s = "151D";
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break;
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default:
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cpu_s = "????";
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break;
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}
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/* Package */
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switch (get_cpu_package()) {
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case PKG_AA_LFBGA448:
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pkg = "AA";
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break;
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case PKG_AB_LFBGA354:
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pkg = "AB";
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break;
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case PKG_AC_TFBGA361:
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pkg = "AC";
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break;
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case PKG_AD_TFBGA257:
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pkg = "AD";
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break;
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default:
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pkg = "??";
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break;
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}
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/* REVISION */
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switch (stm32mp_get_chip_version()) {
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case STM32MP1_REV_B:
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cpu_r = "B";
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break;
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case STM32MP1_REV_Z:
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cpu_r = "Z";
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break;
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default:
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cpu_r = "?";
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break;
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}
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snprintf(name, STM32_SOC_NAME_SIZE,
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"STM32MP%s%s Rev.%s", cpu_s, pkg, cpu_r);
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}
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void stm32mp_print_cpuinfo(void)
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{
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char name[STM32_SOC_NAME_SIZE];
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stm32mp_get_soc_name(name);
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NOTICE("CPU: %s\n", name);
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}
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void stm32mp_print_boardinfo(void)
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{
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uint32_t board_id;
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uint32_t board_otp;
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int bsec_node, bsec_board_id_node;
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void *fdt;
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const fdt32_t *cuint;
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if (fdt_get_address(&fdt) == 0) {
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panic();
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}
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bsec_node = fdt_node_offset_by_compatible(fdt, -1, DT_BSEC_COMPAT);
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if (bsec_node < 0) {
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return;
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}
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bsec_board_id_node = fdt_subnode_offset(fdt, bsec_node, "board_id");
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if (bsec_board_id_node <= 0) {
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return;
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}
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cuint = fdt_getprop(fdt, bsec_board_id_node, "reg", NULL);
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if (cuint == NULL) {
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panic();
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}
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board_otp = fdt32_to_cpu(*cuint) / sizeof(uint32_t);
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if (bsec_shadow_read_otp(&board_id, board_otp) != BSEC_OK) {
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ERROR("BSEC: PART_NUMBER_OTP Error\n");
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return;
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}
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if (board_id != 0U) {
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char rev[2];
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rev[0] = BOARD_ID2REV(board_id) - 1 + 'A';
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rev[1] = '\0';
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NOTICE("Board: MB%04x Var%u.%u Rev.%s-%02u\n",
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BOARD_ID2NB(board_id),
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BOARD_ID2VARCPN(board_id),
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BOARD_ID2VARFG(board_id),
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rev,
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BOARD_ID2BOM(board_id));
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}
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}
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/* Return true when SoC provides a single Cortex-A7 core, and false otherwise */
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bool stm32mp_is_single_core(void)
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{
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switch (get_part_number()) {
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case STM32MP151A_PART_NB:
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case STM32MP151C_PART_NB:
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case STM32MP151D_PART_NB:
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case STM32MP151F_PART_NB:
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return true;
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default:
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return false;
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}
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}
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/* Return true when device is in closed state */
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bool stm32mp_is_closed_device(void)
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{
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uint32_t value;
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if ((bsec_shadow_register(DATA0_OTP) != BSEC_OK) ||
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(bsec_read_otp(&value, DATA0_OTP) != BSEC_OK)) {
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return true;
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}
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return (value & DATA0_OTP_SECURED) == DATA0_OTP_SECURED;
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}
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uint32_t stm32_iwdg_get_instance(uintptr_t base)
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{
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switch (base) {
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case IWDG1_BASE:
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return IWDG1_INST;
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case IWDG2_BASE:
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return IWDG2_INST;
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default:
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panic();
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}
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}
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uint32_t stm32_iwdg_get_otp_config(uint32_t iwdg_inst)
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{
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uint32_t iwdg_cfg = 0U;
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uint32_t otp_value;
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#if defined(IMAGE_BL2)
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if (bsec_shadow_register(HW2_OTP) != BSEC_OK) {
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panic();
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}
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#endif
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if (bsec_read_otp(&otp_value, HW2_OTP) != BSEC_OK) {
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panic();
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}
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if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_HW_POS)) != 0U) {
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iwdg_cfg |= IWDG_HW_ENABLED;
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}
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if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STOP_POS)) != 0U) {
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iwdg_cfg |= IWDG_DISABLE_ON_STOP;
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}
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if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STANDBY_POS)) != 0U) {
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iwdg_cfg |= IWDG_DISABLE_ON_STANDBY;
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}
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return iwdg_cfg;
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}
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#if defined(IMAGE_BL2)
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uint32_t stm32_iwdg_shadow_update(uint32_t iwdg_inst, uint32_t flags)
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{
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uint32_t otp;
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uint32_t result;
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if (bsec_shadow_read_otp(&otp, HW2_OTP) != BSEC_OK) {
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panic();
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}
|
|
|
|
if ((flags & IWDG_DISABLE_ON_STOP) != 0U) {
|
|
otp |= BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STOP_POS);
|
|
}
|
|
|
|
if ((flags & IWDG_DISABLE_ON_STANDBY) != 0U) {
|
|
otp |= BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STANDBY_POS);
|
|
}
|
|
|
|
result = bsec_write_otp(otp, HW2_OTP);
|
|
if (result != BSEC_OK) {
|
|
return result;
|
|
}
|
|
|
|
/* Sticky lock OTP_IWDG (read and write) */
|
|
if ((bsec_set_sr_lock(HW2_OTP) != BSEC_OK) ||
|
|
(bsec_set_sw_lock(HW2_OTP) != BSEC_OK)) {
|
|
return BSEC_LOCK_FAIL;
|
|
}
|
|
|
|
return BSEC_OK;
|
|
}
|
|
#endif
|
|
|
|
#if STM32MP_USE_STM32IMAGE
|
|
/* Get the non-secure DDR size */
|
|
uint32_t stm32mp_get_ddr_ns_size(void)
|
|
{
|
|
static uint32_t ddr_ns_size;
|
|
uint32_t ddr_size;
|
|
|
|
if (ddr_ns_size != 0U) {
|
|
return ddr_ns_size;
|
|
}
|
|
|
|
ddr_size = dt_get_ddr_size();
|
|
if ((ddr_size <= (STM32MP_DDR_S_SIZE + STM32MP_DDR_SHMEM_SIZE)) ||
|
|
(ddr_size > STM32MP_DDR_MAX_SIZE)) {
|
|
panic();
|
|
}
|
|
|
|
ddr_ns_size = ddr_size - (STM32MP_DDR_S_SIZE + STM32MP_DDR_SHMEM_SIZE);
|
|
|
|
return ddr_ns_size;
|
|
}
|
|
#endif /* STM32MP_USE_STM32IMAGE */
|
|
|
|
void stm32_save_boot_interface(uint32_t interface, uint32_t instance)
|
|
{
|
|
uint32_t bkpr_itf_idx = tamp_bkpr(TAMP_BOOT_MODE_BACKUP_REG_ID);
|
|
|
|
clk_enable(RTCAPB);
|
|
|
|
mmio_clrsetbits_32(bkpr_itf_idx,
|
|
TAMP_BOOT_MODE_ITF_MASK,
|
|
((interface << 4) | (instance & 0xFU)) <<
|
|
TAMP_BOOT_MODE_ITF_SHIFT);
|
|
|
|
clk_disable(RTCAPB);
|
|
}
|
|
|
|
void stm32_get_boot_interface(uint32_t *interface, uint32_t *instance)
|
|
{
|
|
static uint32_t itf;
|
|
|
|
if (itf == 0U) {
|
|
uint32_t bkpr = tamp_bkpr(TAMP_BOOT_MODE_BACKUP_REG_ID);
|
|
|
|
clk_enable(RTCAPB);
|
|
|
|
itf = (mmio_read_32(bkpr) & TAMP_BOOT_MODE_ITF_MASK) >>
|
|
TAMP_BOOT_MODE_ITF_SHIFT;
|
|
|
|
clk_disable(RTCAPB);
|
|
}
|
|
|
|
*interface = itf >> 4;
|
|
*instance = itf & 0xFU;
|
|
}
|
|
|
|
#if !STM32MP_USE_STM32IMAGE && PSA_FWU_SUPPORT
|
|
void stm32mp1_fwu_set_boot_idx(void)
|
|
{
|
|
clk_enable(RTCAPB);
|
|
mmio_write_32(tamp_bkpr(TAMP_BOOT_COUNTER_REG_ID),
|
|
plat_fwu_get_boot_idx());
|
|
clk_disable(RTCAPB);
|
|
}
|
|
#endif /* !STM32MP_USE_STM32IMAGE && PSA_FWU_SUPPORT */
|