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https://github.com/ARM-software/arm-trusted-firmware.git
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072d7532d2
Rename driver file to BSEC2. Split header file in IP and feature parts. Add functions to access BSEC scratch register. Several corrections and improvements. Probe the driver earlier, especially to check debug features. Change-Id: I1981536398d598d67a19d2d7766dacc18de72ec1 Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com>
129 lines
3.4 KiB
C
129 lines
3.4 KiB
C
/*
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* Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef BSEC_H
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#define BSEC_H
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#include <stdbool.h>
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#include <stdint.h>
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#include <lib/utils_def.h>
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/*
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* IP configuration
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*/
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#define BSEC_OTP_MASK GENMASK(4, 0)
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#define BSEC_OTP_BANK_SHIFT 5
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#define BSEC_TIMEOUT_VALUE 0xFFFF
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/*
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* Return status
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*/
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#define BSEC_OK 0U
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#define BSEC_ERROR 0xFFFFFFFFU
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#define BSEC_DISTURBED 0xFFFFFFFEU
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#define BSEC_INVALID_PARAM 0xFFFFFFFCU
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#define BSEC_PROG_FAIL 0xFFFFFFFBU
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#define BSEC_LOCK_FAIL 0xFFFFFFFAU
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#define BSEC_TIMEOUT 0xFFFFFFF9U
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#define BSEC_RETRY 0xFFFFFFF8U
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#define BSEC_NOT_SUPPORTED 0xFFFFFFF7U
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#define BSEC_WRITE_LOCKED 0xFFFFFFF6U
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#define BSEC_ERROR_INVALID_FVR 0xFFFFFFF5U
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/*
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* OTP MODE
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*/
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#define BSEC_MODE_OPEN1 0x00U
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#define BSEC_MODE_SECURED 0x01U
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#define BSEC_MODE_OPEN2 0x02U
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#define BSEC_MODE_INVALID 0x04U
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/*
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* OTP Lock services definition.
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* Value must corresponding to the bit number in the register.
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* Special case: (bit number << 1) for BSEC3.
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*/
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#define BSEC_LOCK_UPPER_OTP 0x00
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#define BSEC_LOCK_GWLOCK 0x01
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#define BSEC_LOCK_DEBUG 0x02
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#define BSEC_LOCK_PROGRAM 0x03
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#define BSEC_LOCK_KVLOCK 0x04
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/*
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* Values for struct bsec_config::freq
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*/
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#define FREQ_10_20_MHZ 0x0
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#define FREQ_20_30_MHZ 0x1
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#define FREQ_30_45_MHZ 0x2
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#define FREQ_45_67_MHZ 0x3
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/*
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* Device info structure, providing device-specific functions and a means of
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* adding driver-specific state.
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*/
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struct bsec_config {
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uint8_t den_lock; /*
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* Debug enable sticky lock
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* 1 debug enable is locked until next reset
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*/
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/* BSEC2 only */
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uint8_t tread; /* SAFMEM Reading current level default 0 */
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uint8_t pulse_width; /* SAFMEM Programming pulse width default 1 */
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uint8_t freq; /*
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* SAFMEM CLOCK see freq value define
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* default FREQ_45_67_MHZ
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*/
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uint8_t power; /* Power up SAFMEM. 1 power up, 0 power off */
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uint8_t prog_lock; /*
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* Programming Sticky lock
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* 1 programming is locked until next reset
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*/
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uint8_t upper_otp_lock; /*
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* Shadowing of upper OTP sticky lock
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* 1 shadowing of upper OTP is locked
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* until next reset
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*/
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};
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uint32_t bsec_probe(void);
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uint32_t bsec_get_base(void);
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uint32_t bsec_set_config(struct bsec_config *cfg);
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uint32_t bsec_get_config(struct bsec_config *cfg);
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uint32_t bsec_shadow_register(uint32_t otp);
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uint32_t bsec_read_otp(uint32_t *val, uint32_t otp);
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uint32_t bsec_write_otp(uint32_t val, uint32_t otp);
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uint32_t bsec_program_otp(uint32_t val, uint32_t otp);
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uint32_t bsec_permanent_lock_otp(uint32_t otp);
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void bsec_write_debug_conf(uint32_t val);
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uint32_t bsec_read_debug_conf(void);
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void bsec_write_scratch(uint32_t val);
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uint32_t bsec_read_scratch(void);
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uint32_t bsec_get_status(void);
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uint32_t bsec_get_hw_conf(void);
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uint32_t bsec_get_version(void);
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uint32_t bsec_get_id(void);
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uint32_t bsec_get_magic_id(void);
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uint32_t bsec_set_sr_lock(uint32_t otp);
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uint32_t bsec_read_sr_lock(uint32_t otp, bool *value);
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uint32_t bsec_set_sw_lock(uint32_t otp);
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uint32_t bsec_read_sw_lock(uint32_t otp, bool *value);
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uint32_t bsec_set_sp_lock(uint32_t otp);
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uint32_t bsec_read_sp_lock(uint32_t otp, bool *value);
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uint32_t bsec_read_permanent_lock(uint32_t otp, bool *value);
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uint32_t bsec_otp_lock(uint32_t service);
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uint32_t bsec_shadow_read_otp(uint32_t *otp_value, uint32_t word);
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uint32_t bsec_check_nsec_access_rights(uint32_t otp);
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#endif /* BSEC_H */
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