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https://github.com/ARM-software/arm-trusted-firmware.git
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ee2e99c3e3
We no longer maintain the device equipped with ES chip. Remove SPM support for ES ship. Signed-off-by: Wenzhen Yu <wenzhen.yu@mediatek.com> Change-Id: I5b2d035ec384a9861239f33dbe6df54c17f1285c
142 lines
4.1 KiB
C
142 lines
4.1 KiB
C
/*
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* Copyright (c) 2025, Mediatek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MT_SPM_H
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#define MT_SPM_H
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#include <stdint.h>
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#include <stdio.h>
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#include <lib/pm/mtk_pm.h>
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#include <lpm_v2/mt_lp_rq.h>
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#ifdef __GNUC__
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#define spm_likely(x) __builtin_expect(!!(x), 1)
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#define spm_unlikely(x) __builtin_expect(!!(x), 0)
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#else
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#define spm_likely(x) (x)
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#define spm_unlikely(x) (x)
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#endif
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#define CLK_SCP_CFG_0 (CKSYS_BASE + 0x1A0)
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#define INFRA_BUS_DCM_CTRL (INFRACFG_AO_BASE + 0x070)
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#define RG_AXI_DCM_DIS_EN BIT(21)
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#define RG_PLLCK_SEL_NO_SPM BIT(22)
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#define MT_SPM_TIME_GET(tm) ({ (tm) = el3_uptime(); })
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#define SPM_FW_NO_RESUME 1
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#define MCUSYS_MTCMOS_ON 0
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#define WAKEUP_LOG_ON 0
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#define MT_SPM_USING_SRCLKEN_RC
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/* SPM extern operand definition */
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#define MT_SPM_EX_OP_CLR_26M_RECORD BIT(0)
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#define MT_SPM_EX_OP_SET_WDT BIT(1)
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#define MT_SPM_EX_OP_NON_GENERIC_RESOURCE_REQ BIT(2)
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#define MT_SPM_EX_OP_SET_SUSPEND_MODE BIT(3)
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#define MT_SPM_EX_OP_SET_IS_ADSP BIT(4)
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#define MT_SPM_EX_OP_SRCLKEN_RC_BBLPM BIT(5)
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#define MT_SPM_EX_OP_HW_S1_DETECT BIT(6)
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#define MT_SPM_EX_OP_TRACE_LP BIT(7)
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#define MT_SPM_EX_OP_TRACE_SUSPEND BIT(8)
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#define MT_SPM_EX_OP_TRACE_TIMESTAMP_EN BIT(9)
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#define MT_SPM_EX_OP_TIME_CHECK BIT(10)
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#define MT_SPM_EX_OP_TIME_OBS BIT(11)
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#define MT_SPM_EX_OP_SET_IS_USB_HEADSET BIT(12)
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#define MT_SPM_EX_OP_SET_IS_FM_AUDIO BIT(13)
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#define MT_SPM_EX_OP_DEVICES_SAVE BIT(14)
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#define MT_SPM_EX_OP_NOTIFY_INFRA_OFF BIT(15)
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#define MT_BUS26M_EXT_LP_26M_ON_MODE (MT_SPM_EX_OP_SET_IS_ADSP | \
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MT_SPM_EX_OP_SET_IS_FM_AUDIO)
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#define MT_VCORE_EXT_LP_VCORE_ON_MODE (MT_SPM_EX_OP_SET_IS_ADSP | \
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MT_SPM_EX_OP_SET_IS_FM_AUDIO)
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/* EN SPM INFRA DEBUG OUT */
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#define DEBUGSYS_DEBUG_EN_REG (DBGSYS_DEM_BASE + 0x94)
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/* INFRA_AO_DEBUG_CON */
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#define INFRA_AO_DBG_CON0 (INFRACFG_AO_BASE + 0x500)
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#define INFRA_AO_DBG_CON1 (INFRACFG_AO_BASE + 0x504)
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#define INFRA_AO_DBG_CON2 (INFRACFG_AO_BASE + 0x508)
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#define INFRA_AO_DBG_CON3 (INFRACFG_AO_BASE + 0x50C)
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/* SPM init. related registers */
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#define VLP_AO_APC_CON (VLP_AO_DEVAPC_APB_BASE + 0xF00)
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#define VLP_AO_MAS_SEC_0 (VLP_AO_DEVAPC_APB_BASE + 0xA00)
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#define SCP_CFGREG_PERI_BUS_CTRL0 (SCP_CFGREG_BASE + 0x24)
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#define MODULE_SW_CG_0_MASK (INFRACFG_AO_BASE + 0x060)
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#define VLP_DBG_MON_SEL0_ADDR (VLPCFG_BUS_BASE + 0x108)
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#define VLP_DBG_MON_SEL1_ADDR (VLPCFG_BUS_BASE + 0x10C)
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#define VLP_CLKSQ_CON1 (VLP_CKSYS_BASE + 0x224)
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#define VLP_AP_PLL_CON3 (VLP_CKSYS_BASE + 0x264)
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/* SPM SRAM Data */
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#define SPM_SRAM_TIMESTAMP_START (SPM_SRAM_BASE + 0xF80)
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#define SPM_SRAM_TIMESTAMP_END (SPM_SRAM_BASE + 0xFFC)
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#define SPM_SRAM_TIMESTAMP_SIZE \
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(((SPM_SRAM_TIMESTAMP_END - SPM_SRAM_TIMESTAMP_START) >> 2) + 1)
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/* AP_MDSRC_REQ MD 26M ON settle time (3ms) */
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#define AP_MDSRC_REQ_MD_26M_SETTLE 3
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/* Setting the SPM settle time*/
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#define SPM_SYSCLK_SETTLE 0x60FE /* 1685us */
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/* Setting the SPM req/ack time*/
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#define SPM_ACK_TIMEOUT_US 1000
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/* Settine the firmware status check for SPM PC */
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#define SPM_PC_CHECKABLE
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enum {
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SPM_ARGS_SPMFW_IDX_KICK = 0,
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SPM_ARGS_SPMFW_INIT,
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SPM_ARGS_SUSPEND,
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SPM_ARGS_SUSPEND_FINISH,
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SPM_ARGS_SODI,
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SPM_ARGS_SODI_FINISH,
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SPM_ARGS_DPIDLE,
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SPM_ARGS_DPIDLE_FINISH,
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SPM_ARGS_PCM_WDT,
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SPM_ARGS_SUSPEND_CALLBACK,
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SPM_ARGS_HARDWARE_CG_CHECK,
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SPM_ARGS_NUM,
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};
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typedef enum {
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WR_NONE = 0,
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WR_UART_BUSY,
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WR_ABORT,
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WR_PCM_TIMER,
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WR_WAKE_SRC,
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WR_DVFSRC,
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WR_TWAM,
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WR_PMSR,
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WR_SPM_ACK_CHK,
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WR_UNKNOWN,
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} wake_reason_t;
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struct pwr_ctrl;
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struct spm_lp_scen;
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void spm_set_irq_num(uint32_t num);
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void spm_irq0_handler(uint64_t x1, uint64_t x2);
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struct mt_lp_resource_user *get_spm_res_user(void);
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int mt_spm_common_sodi_get_spm_pcm_flag(uint32_t *lp, uint32_t idx);
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void mt_spm_common_sodi_en(bool en);
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int mt_spm_common_sodi_get_spm_lp(struct spm_lp_scen **lp);
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void mt_spm_set_common_sodi_pwrctr(void);
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void mt_spm_set_common_sodi_pcm_flags(void);
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int spm_boot_init(void);
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void spm_dvfsfw_init(uint64_t boot_up_opp, uint64_t dram_issue);
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extern struct pwr_ctrl spm_init_ctrl;
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/* Support by bl31_plat_setup.c */
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uint32_t is_abnormal_boot(void);
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#endif /* MT_SPM_H */
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