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c3ab09d1c5
Warn users about disabled OCM coherency which is not enabled by default in designs. If it is not enabled and TF-A is running out of OCM,TF-A won't work properly. This check is done only in Debug mode and isolation disabled. Change-Id: I7661e0183503b71085c57fa35014341d14522203 Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>
82 lines
3 KiB
C
82 lines
3 KiB
C
/*
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* Copyright (c) 2025, Advanced Micro Devices, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include <plat_ocm_coherency.h>
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#include <platform_def.h>
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/*
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* Register non hash mem regions addresses
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*/
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#define POR_RNSAM_NODE_INFO_U_RNFBESAM_NID12 U(0xF8168000)
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#define NON_HASH_MEM_REGION_REG0 U(POR_RNSAM_NODE_INFO_U_RNFBESAM_NID12 + 0xC08)
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#define NON_HASH_MEM_REGION_REG1 U(POR_RNSAM_NODE_INFO_U_RNFBESAM_NID12 + 0xC0C)
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#define NON_HASH_MEM_REGION_REG2 U(POR_RNSAM_NODE_INFO_U_RNFBESAM_NID12 + 0xC10)
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#define NON_HASH_MEM_REGION_REG3 U(POR_RNSAM_NODE_INFO_U_RNFBESAM_NID12 + 0xC14)
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#define NON_HASH_MEM_REGION_REG4 U(POR_RNSAM_NODE_INFO_U_RNFBESAM_NID12 + 0xC18)
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#define NON_HASH_MEM_REGION_REG5 U(POR_RNSAM_NODE_INFO_U_RNFBESAM_NID12 + 0xC1C)
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#define NON_HASH_MEM_REGION_REG6 U(POR_RNSAM_NODE_INFO_U_RNFBESAM_NID12 + 0xC20)
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#define NON_HASH_MEM_REGION_REG7 U(POR_RNSAM_NODE_INFO_U_RNFBESAM_NID12 + 0xC24)
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#define REGION_BASE_ADDR_VALUE U(0x2E)
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#define REGION_BASE_ADDR_SHIFT 9
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#define REGION_BASE_ADDRESS_MASK GENMASK(30, REGION_BASE_ADDR_SHIFT)
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#define REGION_VALID_BIT BIT(0)
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/*
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* verify the register configured as non-hashed
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*/
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#define IS_NON_HASHED_REGION(reg) \
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((FIELD_GET(REGION_BASE_ADDRESS_MASK, mmio_read_32(reg)) == REGION_BASE_ADDR_VALUE) && \
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(mmio_read_32(reg) & REGION_VALID_BIT))
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/*
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* Splitter registers
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*/
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#define FPX_SPLITTER_0 U(0xECC20000)
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#define FPX_SPLITTER_1 U(0xECD20000)
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#define FPX_SPLITTER_2 U(0xECE20000)
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#define FPX_SPLITTER_3 U(0xECF20000)
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#define OCM_ADDR_DIST_MODE BIT(16)
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#define OCM_COHERENT 0
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#define OCM_NOT_COHERENT 1
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#define TFA_NOT_IN_OCM 2
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/*
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* Function that verifies the OCM is coherent or not with the following checks:
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* verify that OCM is in non hashed region or not if not then verify
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* OCM_ADDR_DIST_MODE bit in splitter registers is set.
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*/
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int32_t check_ocm_coherency(void)
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{
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int32_t status = OCM_COHERENT;
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/* isolation should be disabled in order to read these registers */
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if ((IS_NON_HASHED_REGION(NON_HASH_MEM_REGION_REG0) ||
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IS_NON_HASHED_REGION(NON_HASH_MEM_REGION_REG1) ||
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IS_NON_HASHED_REGION(NON_HASH_MEM_REGION_REG2) ||
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IS_NON_HASHED_REGION(NON_HASH_MEM_REGION_REG3) ||
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IS_NON_HASHED_REGION(NON_HASH_MEM_REGION_REG4) ||
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IS_NON_HASHED_REGION(NON_HASH_MEM_REGION_REG5) ||
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IS_NON_HASHED_REGION(NON_HASH_MEM_REGION_REG6) ||
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IS_NON_HASHED_REGION(NON_HASH_MEM_REGION_REG7))) {
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WARN("OCM is not configured as coherent\n");
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status = OCM_NOT_COHERENT;
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} else {
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/* verify OCM_ADDR_DIST_MODE bit in splitter registers is set */
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if (!((mmio_read_32(FPX_SPLITTER_0) & OCM_ADDR_DIST_MODE) &&
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(mmio_read_32(FPX_SPLITTER_1) & OCM_ADDR_DIST_MODE) &&
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(mmio_read_32(FPX_SPLITTER_2) & OCM_ADDR_DIST_MODE) &&
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(mmio_read_32(FPX_SPLITTER_3) & OCM_ADDR_DIST_MODE))) {
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WARN("OCM is not configured as coherent\n");
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status = OCM_NOT_COHERENT;
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}
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}
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return status;
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}
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