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![]() Cortex-A720 erratum 3699561 that applies to all revisions <= r0p2 and is still Open. The workaround is for EL3 software that performs context save/restore on a change of Security state to use a value of SCR_EL3.NS when accessing ICH_VMCR_EL2 that reflects the Security state that owns the data being saved or restored. SDEN documentation: https://developer.arm.com/documentation/SDEN-2439421/latest/ Change-Id: I7ea3aaf3e7bf6b4f3648f6872e505a41247b14ba Signed-off-by: Govindraj Raja <govindraj.raja@arm.com> |
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alt-boot-flows.rst | ||
auth-framework.rst | ||
cpu-specific-build-macros.rst | ||
firmware-design.rst | ||
index.rst | ||
interrupt-framework-design.rst | ||
psci-pd-tree.rst | ||
reset-design.rst | ||
trusted-board-boot-build.rst | ||
trusted-board-boot.rst |