mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-16 09:34:18 +00:00
050a99a62f
NXP drivers header files are moved: - from: drivers/nxp/<xx>/*.h - to : include/drivers/nxp/<xx>/*.h To accommodate these changes each drivers makefiles drivers/nxp/<xx>/xx.mk, are updated. Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I3979c509724d87e3d631a03dbafda1ee5ef07d21
72 lines
2.2 KiB
C
72 lines
2.2 KiB
C
/*
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* Copyright 2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef PLAT_GICV2_H
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#define PLAT_GICV2_H
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#include <drivers/arm/gicv2.h>
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/* register offsets */
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#define GICD_CTLR_OFFSET 0x0
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#define GICD_CPENDSGIR3_OFFSET 0xF1C
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#define GICD_SPENDSGIR3_OFFSET 0xF2C
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#define GICD_SGIR_OFFSET 0xF00
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#define GICD_IGROUPR0_OFFSET 0x080
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#define GICD_TYPER_OFFSET 0x0004
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#define GICD_ISENABLER0_OFFSET 0x0100
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#define GICD_ICENABLER0_OFFSET 0x0180
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#define GICD_IPRIORITYR3_OFFSET 0x040C
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#define GICD_ISENABLERn_OFFSET 0x0100
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#define GICD_ISACTIVER0_OFFSET 0x300
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#define GICC_CTLR_OFFSET 0x0
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#define GICC_PMR_OFFSET 0x0004
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#define GICC_IAR_OFFSET 0x000C
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#define GICC_DIR_OFFSET 0x1000
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#define GICC_EOIR_OFFSET 0x0010
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/* bitfield masks */
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#define GICC_CTLR_EN_GRP0 0x1
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#define GICC_CTLR_EN_GRP1 0x2
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#define GICC_CTLR_EOImodeS_MASK 0x200
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#define GICC_CTLR_DIS_BYPASS 0x60
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#define GICC_CTLR_CBPR_MASK 0x10
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#define GICC_CTLR_FIQ_EN_MASK 0x8
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#define GICC_CTLR_ACKCTL_MASK 0x4
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#define GICC_PMR_FILTER 0xFF
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#define GICD_CTLR_EN_GRP0 0x1
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#define GICD_CTLR_EN_GRP1 0x2
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#define GICD_IGROUP0_SGI15 0x8000
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#define GICD_ISENABLE0_SGI15 0x8000
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#define GICD_ICENABLE0_SGI15 0x8000
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#define GICD_ISACTIVER0_SGI15 0x8000
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#define GICD_CPENDSGIR_CLR_MASK 0xFF000000
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#define GICD_IPRIORITY_SGI15_MASK 0xFF000000
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#define GICD_SPENDSGIR3_SGI15_MASK 0xFF000000
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#define GICD_SPENDSGIR3_SGI15_OFFSET 0x18
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#ifndef __ASSEMBLER__
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/* GIC common API's */
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void plat_ls_gic_driver_init(const uintptr_t nxp_gicd_addr,
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const uintptr_t nxp_gicc_addr,
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uint8_t plat_core_count,
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interrupt_prop_t *ls_interrupt_props,
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uint8_t ls_interrupt_prop_count,
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uint32_t *target_mask_array);
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void plat_ls_gic_init(void);
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void plat_ls_gic_cpuif_enable(void);
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void plat_ls_gic_cpuif_disable(void);
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void plat_ls_gic_redistif_on(void);
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void plat_ls_gic_redistif_off(void);
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void plat_gic_pcpu_init(void);
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/* GIC utility functions */
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void get_gic_offset(uint32_t *gicc_base, uint32_t *gicd_base);
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#endif
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#endif /* PLAT_GICV2_H */
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