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https://github.com/ARM-software/arm-trusted-firmware.git
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050a99a62f
NXP drivers header files are moved: - from: drivers/nxp/<xx>/*.h - to : include/drivers/nxp/<xx>/*.h To accommodate these changes each drivers makefiles drivers/nxp/<xx>/xx.mk, are updated. Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I3979c509724d87e3d631a03dbafda1ee5ef07d21
85 lines
1.9 KiB
C
85 lines
1.9 KiB
C
/*
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* Copyright 2018-2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef DCFG_H
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#define DCFG_H
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#include <endian.h>
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#if defined(CONFIG_CHASSIS_2)
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#include <dcfg_lsch2.h>
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#elif defined(CONFIG_CHASSIS_3_2)
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#include <dcfg_lsch3.h>
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#endif
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#ifdef NXP_GUR_BE
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#define gur_in32(a) bswap32(mmio_read_32((uintptr_t)(a)))
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#define gur_out32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v))
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#elif defined(NXP_GUR_LE)
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#define gur_in32(a) mmio_read_32((uintptr_t)(a))
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#define gur_out32(a, v) mmio_write_32((uintptr_t)(a), v)
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#else
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#error Please define CCSR GUR register endianness
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#endif
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typedef struct {
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bool is_populated;
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uint8_t mfr_id;
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#if defined(CONFIG_CHASSIS_3_2)
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uint8_t family;
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uint8_t dev_id;
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#endif
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uint8_t personality;
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bool sec_enabled;
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uint8_t maj_ver;
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uint8_t min_ver;
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} soc_info_t;
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typedef struct {
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bool is_populated;
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uint8_t ocram_present;
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uint8_t ddrc1_present;
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#if defined(CONFIG_CHASSIS_3_2)
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uint8_t ddrc2_present;
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#endif
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} devdisr5_info_t;
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typedef struct {
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uint32_t porsr1;
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uintptr_t g_nxp_dcfg_addr;
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unsigned long nxp_sysclk_freq;
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unsigned long nxp_ddrclk_freq;
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unsigned int nxp_plat_clk_divider;
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} dcfg_init_info_t;
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struct sysinfo {
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unsigned long freq_platform;
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unsigned long freq_ddr_pll0;
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unsigned long freq_ddr_pll1;
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};
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int get_clocks(struct sysinfo *sys);
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/* Read the PORSR1 register */
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uint32_t read_reg_porsr1(void);
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/*******************************************************************************
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* Returns true if secur eboot is enabled on board
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* mode = 0 (development mode - sb_en = 1)
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* mode = 1 (production mode - ITS = 1)
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******************************************************************************/
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bool check_boot_mode_secure(uint32_t *mode);
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const soc_info_t *get_soc_info();
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const devdisr5_info_t *get_devdisr5_info();
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void dcfg_init(dcfg_init_info_t *dcfg_init_data);
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bool is_sec_enabled(void);
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void error_handler(int error_code);
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#endif /* DCFG_H */
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