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https://github.com/ARM-software/arm-trusted-firmware.git
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044bb2faab
The build option `ENABLE_ASSERTIONS` should be used instead. That way both C and ASM assertions can be enabled or disabled together. All occurrences of `ASM_ASSERTION` in common code and ARM platforms have been replaced by `ENABLE_ASSERTIONS`. ASM_ASSERTION has been removed from the user guide. Change-Id: I51f1991f11b9b7ff83e787c9a3270c274748ec6f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
307 lines
8.2 KiB
ArmAsm
307 lines
8.2 KiB
ArmAsm
/*
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* Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <assert_macros.S>
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#ifdef IMAGE_BL31
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#include <cpu_data.h>
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#endif
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#include <cpu_macros.S>
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#include <debug.h>
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#include <errata_report.h>
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/* Reset fn is needed in BL at reset vector */
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#if defined(IMAGE_BL1) || defined(IMAGE_BL31)
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/*
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* The reset handler common to all platforms. After a matching
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* cpu_ops structure entry is found, the correponding reset_handler
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* in the cpu_ops is invoked.
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* Clobbers: x0 - x19, x30
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*/
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.globl reset_handler
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func reset_handler
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mov x19, x30
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/* The plat_reset_handler can clobber x0 - x18, x30 */
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bl plat_reset_handler
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/* Get the matching cpu_ops pointer */
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bl get_cpu_ops_ptr
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#if ENABLE_ASSERTIONS
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cmp x0, #0
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ASM_ASSERT(ne)
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#endif
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/* Get the cpu_ops reset handler */
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ldr x2, [x0, #CPU_RESET_FUNC]
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mov x30, x19
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cbz x2, 1f
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/* The cpu_ops reset handler can clobber x0 - x19, x30 */
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br x2
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1:
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ret
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endfunc reset_handler
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#endif /* IMAGE_BL1 || IMAGE_BL31 */
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#ifdef IMAGE_BL31 /* The power down core and cluster is needed only in BL31 */
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/*
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* void prepare_cpu_pwr_dwn(unsigned int power_level)
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*
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* Prepare CPU power down function for all platforms. The function takes
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* a domain level to be powered down as its parameter. After the cpu_ops
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* pointer is retrieved from cpu_data, the handler for requested power
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* level is called.
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*/
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.globl prepare_cpu_pwr_dwn
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func prepare_cpu_pwr_dwn
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/*
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* If the given power level exceeds CPU_MAX_PWR_DWN_OPS, we call the
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* power down handler for the last power level
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*/
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mov_imm x2, (CPU_MAX_PWR_DWN_OPS - 1)
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cmp x0, x2
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csel x2, x2, x0, hi
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mrs x1, tpidr_el3
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ldr x0, [x1, #CPU_DATA_CPU_OPS_PTR]
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#if ENABLE_ASSERTIONS
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cmp x0, #0
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ASM_ASSERT(ne)
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#endif
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/* Get the appropriate power down handler */
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mov x1, #CPU_PWR_DWN_OPS
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add x1, x1, x2, lsl #3
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ldr x1, [x0, x1]
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br x1
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endfunc prepare_cpu_pwr_dwn
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/*
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* Initializes the cpu_ops_ptr if not already initialized
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* in cpu_data. This can be called without a runtime stack, but may
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* only be called after the MMU is enabled.
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* clobbers: x0 - x6, x10
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*/
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.globl init_cpu_ops
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func init_cpu_ops
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mrs x6, tpidr_el3
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ldr x0, [x6, #CPU_DATA_CPU_OPS_PTR]
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cbnz x0, 1f
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mov x10, x30
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bl get_cpu_ops_ptr
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#if ENABLE_ASSERTIONS
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cmp x0, #0
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ASM_ASSERT(ne)
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#endif
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str x0, [x6, #CPU_DATA_CPU_OPS_PTR]!
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mov x30, x10
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1:
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ret
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endfunc init_cpu_ops
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#endif /* IMAGE_BL31 */
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#if defined(IMAGE_BL31) && CRASH_REPORTING
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/*
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* The cpu specific registers which need to be reported in a crash
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* are reported via cpu_ops cpu_reg_dump function. After a matching
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* cpu_ops structure entry is found, the correponding cpu_reg_dump
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* in the cpu_ops is invoked.
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*/
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.globl do_cpu_reg_dump
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func do_cpu_reg_dump
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mov x16, x30
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/* Get the matching cpu_ops pointer */
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bl get_cpu_ops_ptr
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cbz x0, 1f
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/* Get the cpu_ops cpu_reg_dump */
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ldr x2, [x0, #CPU_REG_DUMP]
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cbz x2, 1f
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blr x2
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1:
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mov x30, x16
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ret
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endfunc do_cpu_reg_dump
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#endif
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/*
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* The below function returns the cpu_ops structure matching the
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* midr of the core. It reads the MIDR_EL1 and finds the matching
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* entry in cpu_ops entries. Only the implementation and part number
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* are used to match the entries.
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* Return :
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* x0 - The matching cpu_ops pointer on Success
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* x0 - 0 on failure.
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* Clobbers : x0 - x5
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*/
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.globl get_cpu_ops_ptr
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func get_cpu_ops_ptr
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/* Get the cpu_ops start and end locations */
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adr x4, (__CPU_OPS_START__ + CPU_MIDR)
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adr x5, (__CPU_OPS_END__ + CPU_MIDR)
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/* Initialize the return parameter */
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mov x0, #0
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/* Read the MIDR_EL1 */
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mrs x2, midr_el1
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mov_imm x3, CPU_IMPL_PN_MASK
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/* Retain only the implementation and part number using mask */
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and w2, w2, w3
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1:
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/* Check if we have reached end of list */
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cmp x4, x5
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b.eq error_exit
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/* load the midr from the cpu_ops */
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ldr x1, [x4], #CPU_OPS_SIZE
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and w1, w1, w3
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/* Check if midr matches to midr of this core */
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cmp w1, w2
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b.ne 1b
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/* Subtract the increment and offset to get the cpu-ops pointer */
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sub x0, x4, #(CPU_OPS_SIZE + CPU_MIDR)
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error_exit:
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ret
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endfunc get_cpu_ops_ptr
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/*
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* Extract CPU revision and variant, and combine them into a single numeric for
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* easier comparison.
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*/
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.globl cpu_get_rev_var
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func cpu_get_rev_var
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mrs x1, midr_el1
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/*
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* Extract the variant[23:20] and revision[3:0] from MIDR, and pack them
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* as variant[7:4] and revision[3:0] of x0.
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*
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* First extract x1[23:16] to x0[7:0] and zero fill the rest. Then
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* extract x1[3:0] into x0[3:0] retaining other bits.
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*/
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ubfx x0, x1, #(MIDR_VAR_SHIFT - MIDR_REV_BITS), #(MIDR_REV_BITS + MIDR_VAR_BITS)
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bfxil x0, x1, #MIDR_REV_SHIFT, #MIDR_REV_BITS
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ret
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endfunc cpu_get_rev_var
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/*
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* Compare the CPU's revision-variant (x0) with a given value (x1), for errata
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* application purposes. If the revision-variant is less than or same as a given
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* value, indicates that errata applies; otherwise not.
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*/
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.globl cpu_rev_var_ls
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func cpu_rev_var_ls
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mov x2, #ERRATA_APPLIES
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mov x3, #ERRATA_NOT_APPLIES
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cmp x0, x1
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csel x0, x2, x3, ls
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ret
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endfunc cpu_rev_var_ls
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/*
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* Compare the CPU's revision-variant (x0) with a given value (x1), for errata
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* application purposes. If the revision-variant is higher than or same as a
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* given value, indicates that errata applies; otherwise not.
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*/
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.globl cpu_rev_var_hs
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func cpu_rev_var_hs
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mov x2, #ERRATA_APPLIES
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mov x3, #ERRATA_NOT_APPLIES
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cmp x0, x1
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csel x0, x2, x3, hs
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ret
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endfunc cpu_rev_var_hs
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#if REPORT_ERRATA
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/*
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* void print_errata_status(void);
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*
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* Function to print errata status for CPUs of its class. Must be called only:
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*
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* - with MMU and data caches are enabled;
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* - after cpu_ops have been initialized in per-CPU data.
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*/
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.globl print_errata_status
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func print_errata_status
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#ifdef IMAGE_BL1
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/*
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* BL1 doesn't have per-CPU data. So retrieve the CPU operations
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* directly.
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*/
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stp xzr, x30, [sp, #-16]!
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bl get_cpu_ops_ptr
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ldp xzr, x30, [sp], #16
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ldr x1, [x0, #CPU_ERRATA_FUNC]
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cbnz x1, .Lprint
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#else
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/*
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* Retrieve pointer to cpu_ops from per-CPU data, and further, the
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* errata printing function. If it's non-NULL, jump to the function in
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* turn.
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*/
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mrs x0, tpidr_el3
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ldr x1, [x0, #CPU_DATA_CPU_OPS_PTR]
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ldr x0, [x1, #CPU_ERRATA_FUNC]
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cbz x0, .Lnoprint
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/*
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* Printing errata status requires atomically testing the printed flag.
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*/
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stp x8, x30, [sp, #-16]!
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mov x8, x0
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/*
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* Load pointers to errata lock and printed flag. Call
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* errata_needs_reporting to check whether this CPU needs to report
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* errata status pertaining to its class.
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*/
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ldr x0, [x1, #CPU_ERRATA_LOCK]
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ldr x1, [x1, #CPU_ERRATA_PRINTED]
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bl errata_needs_reporting
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mov x1, x8
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ldp x8, x30, [sp], #16
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cbnz x0, .Lprint
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#endif
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.Lnoprint:
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ret
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.Lprint:
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/* Jump to errata reporting function for this CPU */
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br x1
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endfunc print_errata_status
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#endif
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