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https://github.com/ARM-software/arm-trusted-firmware.git
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890abc33e4
This patch changes all Rockchip platforms to use the new MULTI_CONSOLE_API. The platform-specific plat_crash_console implementations are removed so that the platform can use the ones from the common platform code instead. Also change the registers used in plat_crash_print_regs. The existing use of x16 and x17 has always been illegal, since those registers are reserved for use by the linker as a temporary scratch registers in intra-procedure-call veneers and can never be expected to maintain their values across a function call. Change-Id: I8249424150be8d5543ed4af93b56756795a5288f Signed-off-by: Julius Werner <jwerner@chromium.org>
129 lines
4.3 KiB
C
129 lines
4.3 KiB
C
/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arm_gic.h>
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#include <assert.h>
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#include <bl_common.h>
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#include <console.h>
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#include <coreboot.h>
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#include <debug.h>
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#include <generic_delay_timer.h>
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#include <mmio.h>
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#include <plat_private.h>
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#include <platform.h>
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#include <platform_def.h>
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#include <uart_16550.h>
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/*******************************************************************************
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* Declarations of linker defined symbols which will help us find the layout
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* of trusted SRAM
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******************************************************************************/
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unsigned long __RO_START__;
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unsigned long __RO_END__;
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/*
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* The next 2 constants identify the extents of the code & RO data region.
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* These addresses are used by the MMU setup code and therefore they must be
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* page-aligned. It is the responsibility of the linker script to ensure that
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* __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
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*/
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#define BL31_RO_BASE (unsigned long)(&__RO_START__)
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#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
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static entry_point_info_t bl32_ep_info;
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static entry_point_info_t bl33_ep_info;
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/*******************************************************************************
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* Return a pointer to the 'entry_point_info' structure of the next image for
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* the security state specified. BL33 corresponds to the non-secure image type
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* while BL32 corresponds to the secure image type. A NULL pointer is returned
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* if the image does not exist.
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******************************************************************************/
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entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
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{
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entry_point_info_t *next_image_info;
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next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info;
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/* None of the images on this platform can have 0x0 as the entrypoint */
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if (next_image_info->pc)
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return next_image_info;
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else
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return NULL;
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}
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#pragma weak params_early_setup
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void params_early_setup(void *plat_param_from_bl2)
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{
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}
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/*******************************************************************************
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* Perform any BL3-1 early platform setup. Here is an opportunity to copy
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* parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they
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* are lost (potentially). This needs to be done before the MMU is initialized
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* so that the memory layout can be used while creating page tables.
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* BL2 has flushed this information to memory, so we are guaranteed to pick up
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* good data.
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******************************************************************************/
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void bl31_early_platform_setup(bl31_params_t *from_bl2,
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void *plat_params_from_bl2)
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{
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static console_16550_t console;
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params_early_setup(plat_params_from_bl2);
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#if COREBOOT
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if (coreboot_serial.type)
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console_16550_register(coreboot_serial.baseaddr,
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coreboot_serial.input_hertz,
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coreboot_serial.baud,
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&console);
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#else
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console_16550_register(PLAT_RK_UART_BASE, PLAT_RK_UART_CLOCK,
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PLAT_RK_UART_BAUDRATE, &console);
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#endif
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VERBOSE("bl31_setup\n");
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/* Passing a NULL context is a critical programming error */
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assert(from_bl2);
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assert(from_bl2->h.type == PARAM_BL31);
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assert(from_bl2->h.version >= VERSION_1);
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bl32_ep_info = *from_bl2->bl32_ep_info;
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bl33_ep_info = *from_bl2->bl33_ep_info;
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}
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/*******************************************************************************
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* Perform any BL3-1 platform setup code
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******************************************************************************/
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void bl31_platform_setup(void)
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{
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generic_delay_timer_init();
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plat_rockchip_soc_init();
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/* Initialize the gic cpu and distributor interfaces */
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plat_rockchip_gic_driver_init();
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plat_rockchip_gic_init();
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plat_rockchip_pmu_init();
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}
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/*******************************************************************************
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* Perform the very early platform specific architectural setup here. At the
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* moment this is only intializes the mmu in a quick and dirty way.
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******************************************************************************/
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void bl31_plat_arch_setup(void)
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{
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plat_cci_init();
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plat_cci_enable();
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plat_configure_mmu_el3(BL31_RO_BASE,
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BL_COHERENT_RAM_END - BL31_RO_BASE,
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BL31_RO_BASE,
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BL31_RO_LIMIT,
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BL_COHERENT_RAM_BASE,
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BL_COHERENT_RAM_END);
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}
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