mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-16 17:44:19 +00:00
1c5f5031f3
coreboot supports an in-memory console to store firmware logs even when no serial console is available. It is widely supported by coreboot-compatible bootloaders (including SeaBIOS and GRUB) and can be read by the Linux kernel. This patch allows BL31 to add its own log messages to this console. The driver will be registered automatically if coreboot support is compiled in and detects the presence of a console buffer in the coreboot tables. Change-Id: I31254dfa0c2fdeb7454634134b5707b4b4154907 Signed-off-by: Julius Werner <jwerner@chromium.org>
123 lines
3 KiB
C
123 lines
3 KiB
C
/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <cbmem_console.h>
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#include <coreboot.h>
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#include <debug.h>
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#include <mmio.h>
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#include <string.h>
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#include <xlat_tables_v2.h>
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/*
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* Structures describing coreboot's in-memory descriptor tables. See
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* <coreboot>/src/commonlib/include/commonlib/coreboot_tables.h for
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* canonical implementation.
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*/
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typedef struct {
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char signature[4];
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uint32_t header_bytes;
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uint32_t header_checksum;
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uint32_t table_bytes;
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uint32_t table_checksum;
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uint32_t table_entries;
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} cb_header_t;
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typedef enum {
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CB_TAG_SERIAL = 0xf,
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CB_TAG_CBMEM_CONSOLE = 0x17,
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} cb_tag_t;
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typedef struct {
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uint32_t tag;
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uint32_t size;
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union {
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coreboot_serial_t serial;
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uint64_t uint64;
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};
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} cb_entry_t;
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coreboot_serial_t coreboot_serial;
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/*
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* The coreboot table is parsed before the MMU is enabled (i.e. with strongly
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* ordered memory), so we cannot make unaligned accesses. The table entries
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* immediately follow one another without padding, so nothing after the header
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* is guaranteed to be naturally aligned. Therefore, we need to define safety
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* functions that can read unaligned integers.
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*/
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static uint32_t read_le32(uint32_t *p)
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{
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uintptr_t addr = (uintptr_t)p;
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return mmio_read_8(addr) |
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mmio_read_8(addr + 1) << 8 |
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mmio_read_8(addr + 2) << 16 |
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mmio_read_8(addr + 3) << 24;
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}
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static uint64_t read_le64(uint64_t *p)
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{
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return read_le32((void *)p) | (uint64_t)read_le32((void *)p + 4) << 32;
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}
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static void expand_and_mmap(uintptr_t baseaddr, size_t size)
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{
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uintptr_t pageaddr = round_down(baseaddr, PAGE_SIZE);
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size_t expanded = round_up(baseaddr - pageaddr + size, PAGE_SIZE);
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mmap_add_region(pageaddr, pageaddr, expanded,
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MT_MEMORY | MT_RW | MT_NS | MT_EXECUTE_NEVER);
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}
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static void setup_cbmem_console(uintptr_t baseaddr)
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{
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static console_cbmc_t console;
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assert(!console.base); /* should only have one CBMEM console */
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/* CBMEM console structure stores its size in first header field. */
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uint32_t size = *(uint32_t *)baseaddr;
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expand_and_mmap(baseaddr, size);
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console_cbmc_register(baseaddr, &console);
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console_set_scope(&console.console, CONSOLE_FLAG_BOOT |
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CONSOLE_FLAG_RUNTIME |
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CONSOLE_FLAG_CRASH);
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}
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void coreboot_table_setup(void *base)
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{
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cb_header_t *header = base;
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void *ptr;
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int i;
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if (strncmp(header->signature, "LBIO", 4)) {
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ERROR("coreboot table signature corrupt!\n");
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return;
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}
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ptr = base + header->header_bytes;
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for (i = 0; i < header->table_entries; i++) {
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cb_entry_t *entry = ptr;
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if (ptr - base >= header->header_bytes + header->table_bytes) {
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ERROR("coreboot table exceeds its bounds!\n");
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break;
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}
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switch (read_le32(&entry->tag)) {
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case CB_TAG_SERIAL:
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memcpy(&coreboot_serial, &entry->serial,
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sizeof(coreboot_serial));
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break;
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case CB_TAG_CBMEM_CONSOLE:
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setup_cbmem_console(read_le64(&entry->uint64));
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break;
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default:
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/* There are many tags TF doesn't need to care about. */
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break;
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}
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ptr += read_le32(&entry->size);
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}
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}
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