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03cd23a10a
This patch de-asserts the CPU reset signals for each CPU as part of it's power on sequence. This is needed to get rid of the wait in BPMP firmware during SC7 exit. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
146 lines
4.1 KiB
C
146 lines
4.1 KiB
C
/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch_helpers.h>
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#include <assert.h>
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#include <debug.h>
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#include <mmio.h>
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#include <platform.h>
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#include <platform_def.h>
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#include <psci.h>
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#include <pmc.h>
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#include <flowctrl.h>
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#include <tegra_def.h>
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#include <tegra_private.h>
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/*
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* Register used to clear CPU reset signals. Each CPU has two reset
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* signals: CPU reset (3:0) and Core reset (19:16).
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*/
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#define CPU_CMPLX_RESET_CLR 0x454
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#define CPU_CORE_RESET_MASK 0x10001
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static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER];
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int tegra_prepare_cpu_suspend(unsigned int id, unsigned int afflvl)
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{
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/* There's nothing to be done for affinity level 1 */
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if (afflvl == MPIDR_AFFLVL1)
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return PSCI_E_SUCCESS;
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switch (id) {
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/* Prepare for cpu idle */
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case PSTATE_ID_CORE_POWERDN:
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tegra_fc_cpu_idle(read_mpidr());
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return PSCI_E_SUCCESS;
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/* Prepare for cluster idle */
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case PSTATE_ID_CLUSTER_IDLE:
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tegra_fc_cluster_idle(read_mpidr());
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return PSCI_E_SUCCESS;
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/* Prepare for cluster powerdn */
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case PSTATE_ID_CLUSTER_POWERDN:
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tegra_fc_cluster_powerdn(read_mpidr());
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return PSCI_E_SUCCESS;
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/* Prepare for system idle */
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case PSTATE_ID_SOC_POWERDN:
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/* Enter system suspend state */
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tegra_pm_system_suspend_entry();
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/* suspend the entire soc */
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tegra_fc_soc_powerdn(read_mpidr());
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return PSCI_E_SUCCESS;
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default:
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ERROR("Unknown state id (%d)\n", id);
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break;
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}
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return PSCI_E_NOT_SUPPORTED;
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}
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int tegra_prepare_cpu_on_finish(unsigned long mpidr)
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{
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/*
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* Check if we are exiting from SOC_POWERDN.
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*/
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if (tegra_system_suspended()) {
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/*
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* Restore Boot and Power Management Processor (BPMP) reset
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* address and reset it.
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*/
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tegra_fc_reset_bpmp();
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/*
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* System resume complete.
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*/
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tegra_pm_system_suspend_exit();
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}
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/*
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* T210 has a dedicated ARMv7 boot and power mgmt processor, BPMP. It's
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* used for power management and boot purposes. Inform the BPMP that
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* we have completed the cluster power up.
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*/
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if (psci_get_max_phys_off_afflvl() == MPIDR_AFFLVL1)
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tegra_fc_lock_active_cluster();
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return PSCI_E_SUCCESS;
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}
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int tegra_prepare_cpu_on(unsigned long mpidr)
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{
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int cpu = mpidr & MPIDR_CPU_MASK;
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uint32_t mask = CPU_CORE_RESET_MASK << cpu;
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/* Deassert CPU reset signals */
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mmio_write_32(TEGRA_CAR_RESET_BASE + CPU_CMPLX_RESET_CLR, mask);
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/* Turn on CPU using flow controller or PMC */
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if (cpu_powergate_mask[cpu] == 0) {
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tegra_pmc_cpu_on(cpu);
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cpu_powergate_mask[cpu] = 1;
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} else {
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tegra_fc_cpu_on(cpu);
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}
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return PSCI_E_SUCCESS;
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}
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int tegra_prepare_cpu_off(unsigned long mpidr)
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{
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tegra_fc_cpu_off(mpidr & MPIDR_CPU_MASK);
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return PSCI_E_SUCCESS;
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}
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