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037a15f5c7
This patch mitigates CVE-2024-7881 [1] by setting CPUACTLR6_EL1[41] to 1 for Neoverse-V3 CPU. [1]: https://developer.arm.com/Arm%20Security%20Center/Arm%20CPU%20Vulnerability%20CVE-2024-7881 Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com> Change-Id: Ib5c644895b8c76d3c7e8b5e6e98d7b9afef7f1ec
106 lines
3.3 KiB
ArmAsm
106 lines
3.3 KiB
ArmAsm
/*
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* Copyright (c) 2022-2025, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <neoverse_v3.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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#include "wa_cve_2022_23960_bhb_vector.S"
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Neoverse V3 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Neoverse V3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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#if WORKAROUND_CVE_2022_23960
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wa_cve_2022_23960_bhb_vector_table NEOVERSE_V3_BHB_LOOP_COUNT, neoverse_v3
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#endif /* WORKAROUND_CVE_2022_23960 */
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/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
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workaround_reset_start neoverse_v3, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
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sysreg_bit_set NEOVERSE_V3_CPUECTLR_EL1, BIT(46)
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workaround_reset_end neoverse_v3, CVE(2024, 5660)
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check_erratum_ls neoverse_v3, CVE(2024, 5660), CPU_REV(0, 1)
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workaround_reset_start neoverse_v3, CVE(2022,23960), WORKAROUND_CVE_2022_23960
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#if IMAGE_BL31
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/*
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* The Neoverse V3 generic vectors are overridden to apply errata
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* mitigation on exception entry from lower ELs.
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*/
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override_vector_table wa_cve_vbar_neoverse_v3
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#endif /* IMAGE_BL31 */
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workaround_reset_end neoverse_v3, CVE(2022,23960)
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check_erratum_chosen neoverse_v3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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workaround_reset_start neoverse_v3, CVE(2024, 7881), WORKAROUND_CVE_2024_7881
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/* ---------------------------------
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* Sets BIT41 of CPUACTLR6_EL1 which
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* disables L1 Data cache prefetcher
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* ---------------------------------
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*/
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sysreg_bit_set NEOVERSE_V3_CPUACTLR6_EL1, BIT(41)
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workaround_reset_end neoverse_v3, CVE(2024, 7881)
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check_erratum_chosen neoverse_v3, CVE(2024, 7881), WORKAROUND_CVE_2024_7881
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/* ---------------------------------------------
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* HW will do the cache maintenance while powering down
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* ---------------------------------------------
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*/
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func neoverse_v3_core_pwr_dwn
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/* ---------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------
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*/
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sysreg_bit_set NEOVERSE_V3_CPUPWRCTLR_EL1, \
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NEOVERSE_V3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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isb
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ret
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endfunc neoverse_v3_core_pwr_dwn
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cpu_reset_func_start neoverse_v3
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/* Disable speculative loads */
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msr SSBS, xzr
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cpu_reset_func_end neoverse_v3
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/* ---------------------------------------------
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* This function provides Neoverse V3 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.neoverse_v3_regs, "aS"
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neoverse_v3_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func neoverse_v3_cpu_reg_dump
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adr x6, neoverse_v3_regs
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mrs x8, NEOVERSE_V3_CPUECTLR_EL1
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ret
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endfunc neoverse_v3_cpu_reg_dump
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declare_cpu_ops neoverse_v3, NEOVERSE_V3_VNAE_MIDR, \
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neoverse_v3_reset_func, \
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neoverse_v3_core_pwr_dwn
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declare_cpu_ops neoverse_v3, NEOVERSE_V3_MIDR, \
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neoverse_v3_reset_func, \
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neoverse_v3_core_pwr_dwn
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