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037a15f5c7
This patch mitigates CVE-2024-7881 [1] by setting CPUACTLR6_EL1[41] to 1 for Neoverse-V3 CPU. [1]: https://developer.arm.com/Arm%20Security%20Center/Arm%20CPU%20Vulnerability%20CVE-2024-7881 Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com> Change-Id: Ib5c644895b8c76d3c7e8b5e6e98d7b9afef7f1ec
33 lines
1.2 KiB
C
33 lines
1.2 KiB
C
/*
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* Copyright (c) 2022-2025, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef NEOVERSE_V3_H
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#define NEOVERSE_V3_H
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#define NEOVERSE_V3_VNAE_MIDR U(0x410FD830)
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#define NEOVERSE_V3_MIDR U(0x410FD840)
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/* Neoverse V3 loop count for CVE-2022-23960 mitigation */
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#define NEOVERSE_V3_BHB_LOOP_COUNT U(132)
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define NEOVERSE_V3_CPUECTLR_EL1 S3_0_C15_C1_4
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/*******************************************************************************
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* CPU Power Control register specific definitions
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******************************************************************************/
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#define NEOVERSE_V3_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define NEOVERSE_V3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
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/*******************************************************************************
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* CPU Auxiliary control register 6 specific definitions
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******************************************************************************/
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#define NEOVERSE_V3_CPUACTLR6_EL1 S3_0_C15_C8_1
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#endif /* NEOVERSE_V3_H */
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