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Erratum 1688305 is a Cat B erratum present in r0p0, r0p1 versions of Hercules core. The erratum can be avoided by setting bit 1 of the implementation defined register CPUACTLR2_EL1 to 1 to prevent store- release from being dispatched before it is the oldest. Change-Id: I2ac04f5d9423868b6cdd4ceb3d0ffa46e570efed Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
44 lines
1.7 KiB
C
44 lines
1.7 KiB
C
/*
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* Copyright (c) 2019, ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_HERCULES_H
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#define CORTEX_HERCULES_H
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#include <lib/utils_def.h>
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#define CORTEX_HERCULES_MIDR U(0x410FD410)
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define CORTEX_HERCULES_CPUECTLR_EL1 S3_0_C15_C1_4
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/*******************************************************************************
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* CPU Power Control register specific definitions
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******************************************************************************/
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#define CORTEX_HERCULES_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_HERCULES_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1)
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_HERCULES_ACTLR_TAM_BIT (ULL(1) << 30)
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#define CORTEX_HERCULES_ACTLR2_EL1 S3_0_C15_C1_1
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#define CORTEX_HERCULES_ACTLR2_EL1_BIT_1 (ULL(1) << 1)
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/*******************************************************************************
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* CPU Activity Monitor Unit register specific definitions.
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******************************************************************************/
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#define CPUAMCNTENCLR0_EL0 S3_3_C15_C2_4
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#define CPUAMCNTENSET0_EL0 S3_3_C15_C2_5
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#define CPUAMCNTENCLR1_EL0 S3_3_C15_C3_0
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#define CPUAMCNTENSET1_EL0 S3_3_C15_C3_1
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#define CORTEX_HERCULES_AMU_GROUP0_MASK U(0xF)
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#define CORTEX_HERCULES_AMU_GROUP1_MASK U(0x7)
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#endif /* CORTEX_HERCULES_H */
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