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https://github.com/ARM-software/arm-trusted-firmware.git
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03396c435a
This patch reworks FVP specific code responsible for determining the entry point information for BL3-2 and BL3-3 stages when BL3-1 is configured as the reset handler. Change-Id: Ia661ff0a6a44c7aabb0b6c1684b2e8d3642d11ec
89 lines
3.4 KiB
Makefile
89 lines
3.4 KiB
Makefile
#
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# Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are met:
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#
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# Redistributions of source code must retain the above copyright notice, this
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# list of conditions and the following disclaimer.
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#
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# Redistributions in binary form must reproduce the above copyright notice,
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# this list of conditions and the following disclaimer in the documentation
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# and/or other materials provided with the distribution.
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#
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# Neither the name of ARM nor the names of its contributors may be used
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# to endorse or promote products derived from this software without specific
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# prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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# POSSIBILITY OF SUCH DAMAGE.
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#
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# On FVP, the TSP can execute either from Trusted SRAM or Trusted DRAM.
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# Trusted SRAM is the default.
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TSP_RAM_LOCATION := tsram
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ifeq (${TSP_RAM_LOCATION}, tsram)
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TSP_RAM_LOCATION_ID := TSP_IN_TZRAM
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else ifeq (${TSP_RAM_LOCATION}, tdram)
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TSP_RAM_LOCATION_ID := TSP_IN_TZDRAM
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else
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$(error "Unsupported TSP_RAM_LOCATION value")
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endif
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# Process TSP_RAM_LOCATION_ID flag
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$(eval $(call add_define,TSP_RAM_LOCATION_ID))
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PLAT_INCLUDES := -Iplat/fvp/include/
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PLAT_BL_COMMON_SOURCES := drivers/arm/pl011/pl011.c \
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drivers/arm/pl011/pl011_console.c \
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drivers/io/io_fip.c \
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drivers/io/io_memmap.c \
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drivers/io/io_semihosting.c \
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lib/mmio.c \
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lib/aarch64/xlat_tables.c \
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lib/semihosting/semihosting.c \
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lib/semihosting/aarch64/semihosting_call.S \
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plat/common/aarch64/plat_common.c \
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plat/fvp/fvp_io_storage.c
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BL1_SOURCES += drivers/arm/cci400/cci400.c \
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plat/common/aarch64/platform_up_stack.S \
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plat/fvp/bl1_fvp_setup.c \
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plat/fvp/aarch64/fvp_common.c \
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plat/fvp/aarch64/fvp_helpers.S
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BL2_SOURCES += drivers/arm/tzc400/tzc400.c \
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plat/common/aarch64/platform_up_stack.S \
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plat/fvp/bl2_fvp_setup.c \
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plat/fvp/fvp_security.c \
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plat/fvp/aarch64/fvp_common.c
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BL31_SOURCES += drivers/arm/cci400/cci400.c \
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drivers/arm/gic/gic_v2.c \
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drivers/arm/gic/gic_v3.c \
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drivers/arm/tzc400/tzc400.c \
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plat/common/aarch64/platform_mp_stack.S \
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plat/fvp/bl31_fvp_setup.c \
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plat/fvp/fvp_gic.c \
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plat/fvp/fvp_pm.c \
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plat/fvp/fvp_security.c \
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plat/fvp/fvp_topology.c \
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plat/fvp/aarch64/fvp_helpers.S \
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plat/fvp/aarch64/fvp_common.c \
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plat/fvp/drivers/pwrc/fvp_pwrc.c
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# Flag used by the FVP port to determine the version of ARM GIC architecture
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# to use for interrupt management in EL3.
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FVP_GIC_ARCH := 2
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$(eval $(call add_define,FVP_GIC_ARCH))
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