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https://github.com/ARM-software/arm-trusted-firmware.git
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010d6ae338
px30 is a Quad-core soc and Cortex-a53 inside. This patch supports the following functions: 1. basic platform setup 2. power up/off cpus 3. suspend/resume cpus 4. suspend/resume system 5. reset system 6. power off system Change-Id: I73d55aa978096c078242be921abe0ddca9e8f67e Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
172 lines
4.7 KiB
C
172 lines
4.7 KiB
C
/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __SOC_H__
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#define __SOC_H__
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#include <plat_private.h>
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#ifndef BITS_WMSK
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#define BITS_WMSK(msk, shift) ((msk) << (shift + REG_MSK_SHIFT))
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#endif
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enum plls_id {
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APLL_ID = 0,
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DPLL_ID,
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CPLL_ID,
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NPLL_ID,
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GPLL_ID,
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END_PLL_ID,
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};
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enum pll_mode {
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SLOW_MODE,
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NORM_MODE,
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DEEP_SLOW_MODE,
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};
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/***************************************************************************
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* SGRF
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***************************************************************************/
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#define SGRF_SOC_CON(i) ((i) * 0x4)
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#define SGRF_DMAC_CON(i) (0x30 + (i) * 0x4)
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#define SGRF_MST_S_ALL_NS 0xffffffff
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#define SGRF_SLV_S_ALL_NS 0xffff0000
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#define DMA_IRQ_BOOT_NS 0xffffffff
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#define DMA_PERI_CH_NS_15_0 0xffffffff
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#define DMA_PERI_CH_NS_19_16 0x000f000f
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#define DMA_MANAGER_BOOT_NS 0x00010001
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#define DMA_SOFTRST_REQ BITS_WITH_WMASK(1, 0x1, 12)
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#define DMA_SOFTRST_RLS BITS_WITH_WMASK(0, 0x1, 12)
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/***************************************************************************
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* GRF
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***************************************************************************/
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#define GRF_SOC_CON(i) (0x0400 + (i) * 4)
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#define GRF_PD_VO_CON0 0x0434
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#define GRF_SOC_STATUS0 0x0480
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#define GRF_CPU_STATUS0 0x0520
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#define GRF_CPU_STATUS1 0x0524
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#define GRF_SOC_NOC_CON0 0x0530
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#define GRF_SOC_NOC_CON1 0x0534
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#define CKECK_WFE_MSK 0x1
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#define CKECK_WFI_MSK 0x10
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#define CKECK_WFEI_MSK 0x11
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#define GRF_SOC_CON2_NSWDT_RST_EN 12
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/***************************************************************************
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* DDR FIREWALL
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***************************************************************************/
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#define FIREWALL_DDR_FW_DDR_RGN(i) ((i) * 0x4)
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#define FIREWALL_DDR_FW_DDR_MST(i) (0x20 + (i) * 0x4)
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#define FIREWALL_DDR_FW_DDR_CON_REG 0x40
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#define FIREWALL_DDR_FW_DDR_RGN_NUM 8
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#define FIREWALL_DDR_FW_DDR_MST_NUM 6
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#define PLAT_MAX_DDR_CAPACITY_MB 4096
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#define RG_MAP_SECURE(top, base) ((((top) - 1) << 16) | (base))
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/***************************************************************************
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* cru
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***************************************************************************/
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#define CRU_MODE 0xa0
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#define CRU_MISC 0xa4
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#define CRU_GLB_CNT_TH 0xb0
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#define CRU_GLB_RST_ST 0xb4
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#define CRU_GLB_SRST_FST 0xb8
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#define CRU_GLB_SRST_SND 0xbc
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#define CRU_GLB_RST_CON 0xc0
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#define CRU_CLKSEL_CON 0x100
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#define CRU_CLKSELS_CON(i) (CRU_CLKSEL_CON + (i) * 4)
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#define CRU_CLKSEL_CON_CNT 60
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#define CRU_CLKGATE_CON 0x200
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#define CRU_CLKGATES_CON(i) (CRU_CLKGATE_CON + (i) * 4)
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#define CRU_CLKGATES_CON_CNT 18
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#define CRU_SOFTRST_CON 0x300
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#define CRU_SOFTRSTS_CON(n) (CRU_SOFTRST_CON + ((n) * 4))
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#define CRU_SOFTRSTS_CON_CNT 12
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#define CRU_AUTOCS_CON0(id) (0x400 + (id) * 8)
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#define CRU_AUTOCS_CON1(id) (0x404 + (id) * 8)
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#define CRU_CONS_GATEID(i) (16 * (i))
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#define GATE_ID(reg, bit) ((reg) * 16 + (bit))
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#define CRU_GLB_SRST_FST_VALUE 0xfdb9
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#define CRU_GLB_SRST_SND_VALUE 0xeca8
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#define CRU_GLB_RST_TSADC_EXT 6
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#define CRU_GLB_RST_WDT_EXT 7
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#define CRU_GLB_CNT_RST_MSK 0xffff
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#define CRU_GLB_CNT_RST_1MS 0x5DC0
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#define CRU_GLB_RST_TSADC_FST BIT(0)
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#define CRU_GLB_RST_WDT_FST BIT(1)
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/***************************************************************************
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* pll
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***************************************************************************/
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#define CRU_PLL_CONS(id, i) ((id) * 0x20 + (i) * 4)
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#define PLL_CON(i) ((i) * 4)
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#define PLL_CON_CNT 5
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#define PLL_LOCK_MSK BIT(10)
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#define PLL_MODE_SHIFT(id) ((id) == CPLL_ID ? \
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2 : \
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((id) == DPLL_ID ? 4 : 2 * (id)))
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#define PLL_MODE_MSK(id) (0x3 << PLL_MODE_SHIFT(id))
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#define PLL_LOCKED_TIMEOUT 600000U
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/***************************************************************************
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* GPIO
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***************************************************************************/
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#define SWPORTA_DR 0x00
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#define SWPORTA_DDR 0x04
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#define GPIO_INTEN 0x30
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#define GPIO_INT_STATUS 0x40
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#define GPIO_NUMS 4
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/**************************************************
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* secure timer
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**************************************************/
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/* chanal0~5 */
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#define STIMER_CHN_BASE(n) (STIME_BASE + 0x20 * (n))
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#define TIMER_LOAD_COUNT0 0x0
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#define TIMER_LOAD_COUNT1 0x4
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#define TIMER_CUR_VALUE0 0x8
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#define TIMER_CUR_VALUE1 0xc
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#define TIMER_CONTROL_REG 0x10
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#define TIMER_INTSTATUS 0x18
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#define TIMER_DIS 0x0
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#define TIMER_EN 0x1
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#define TIMER_FMODE (0x0 << 1)
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#define TIMER_RMODE (0x1 << 1)
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#define TIMER_LOAD_COUNT0_MSK (0xffffffff)
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#define TIMER_LOAD_COUNT1_MSK (0xffffffff00000000)
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void clk_gate_con_save(uint32_t *clkgt_save);
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void clk_gate_con_restore(uint32_t *clkgt_save);
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void clk_gate_con_disable(void);
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void secure_timer_init(void);
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void secure_timer_disable(void);
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void px30_soc_reset_config(void);
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#endif /* __SOC_H__ */
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