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https://github.com/ARM-software/arm-trusted-firmware.git
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00c7d5aca3
This patch adds support for Cortex-A5 FVP for the DesignStart program. DesignStart aims at providing low cost and fast access to Arm IP. Currently with this patch only the primary CPU is booted and the rest of them wait for an interrupt. Signed-off-by: Usama Arif <usama.arif@arm.com> Change-Id: I3a2281ce6de2402dda4610a89939ed53aa045fab
95 lines
1.9 KiB
Text
95 lines
1.9 KiB
Text
/*
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* Copyright (c) 2019, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/dts-v1/;
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/ {
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model = "A5DS";
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compatible = "arm,A5DS";
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a5";
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reg = <0>;
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};
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x80000000 0x7F000000>;
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};
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refclk100mhz: refclk100mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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clock-output-names = "apb_pclk";
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};
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smbclk: refclk24mhzx2 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <48000000>;
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clock-output-names = "smclk";
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};
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rtc@1a220000 {
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compatible = "arm,pl031", "arm,primecell";
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reg = <0x1a220000 0x1000>;
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clocks = <&refclk100mhz>;
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interrupts = <0 6 0xf04>;
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clock-names = "apb_pclk";
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};
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gic: interrupt-controller@1c001000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x1c001000 0x1000>,
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<0x1c000100 0x100>;
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interrupts = <1 9 0xf04>;
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};
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serial0: uart@1a200000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x1a200000 0x1000>;
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interrupt-parent = <&gic>;
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interrupts = <0 8 0xf04>;
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clocks = <&refclk100mhz>;
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clock-names = "apb_pclk";
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};
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serial1: uart@1a210000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x1a210000 0x1000>;
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interrupt-parent = <&gic>;
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interrupts = <0 9 0xf04>;
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clocks = <&refclk100mhz>;
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clock-names = "apb_pclk";
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};
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timer0: timer@1a040000 {
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compatible = "arm,armv7-timer-mem";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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reg = <0x1a040000 0x1000>;
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clock-frequency = <50000000>;
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frame@1a050000 {
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frame-number = <0>;
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interrupts = <0 2 0xf04>;
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reg = <0x1a050000 0x1000>;
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};
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};
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};
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