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05f667f0c6
Third instance of cactus is a UP SP. Set its vcpu count to 1. Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Change-Id: I34b7feb2915e6d335e690e89dea466e75944ed1b
118 lines
2.1 KiB
Text
118 lines
2.1 KiB
Text
/*
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* Copyright (c) 2020-2021, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/dts-v1/;
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/ {
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compatible = "arm,ffa-core-manifest-1.0";
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#address-cells = <2>;
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#size-cells = <1>;
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attribute {
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spmc_id = <0x8000>;
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maj_ver = <0x1>;
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min_ver = <0x0>;
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exec_state = <0x0>;
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load_address = <0x0 0xfd000000>;
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entrypoint = <0x0 0xfd000000>;
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binary_size = <0x80000>;
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};
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hypervisor {
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compatible = "hafnium,hafnium";
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vm1 {
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is_ffa_partition;
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debug_name = "cactus-primary";
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load_address = <0xfe000000>;
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vcpu_count = <8>;
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mem_size = <1048576>;
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};
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vm2 {
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is_ffa_partition;
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debug_name = "cactus-secondary";
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load_address = <0xfe100000>;
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vcpu_count = <8>;
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mem_size = <1048576>;
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};
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vm3 {
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is_ffa_partition;
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debug_name = "cactus-tertiary";
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load_address = <0xfe200000>;
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vcpu_count = <1>;
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mem_size = <1048576>;
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};
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};
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cpus {
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#address-cells = <0x2>;
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#size-cells = <0x0>;
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CPU0:cpu@0 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x0>;
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enable-method = "psci";
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};
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/*
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* SPMC (Hafnium) requires secondary cpu nodes are declared in
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* descending order
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*/
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CPU7:cpu@700 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x700>;
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enable-method = "psci";
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};
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CPU6:cpu@600 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x600>;
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enable-method = "psci";
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};
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CPU5:cpu@500 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x500>;
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enable-method = "psci";
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};
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CPU4:cpu@400 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x400>;
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enable-method = "psci";
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};
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CPU3:cpu@300 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x300>;
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enable-method = "psci";
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};
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CPU2:cpu@200 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x200>;
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enable-method = "psci";
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};
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CPU1:cpu@100 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x100>;
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enable-method = "psci";
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};
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};
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/* 32MB of TC0_TZC_DRAM1_BASE */
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memory@fd000000 {
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device_type = "memory";
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reg = <0x0 0xfd000000 0x2000000>;
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};
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};
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