mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-17 01:54:22 +00:00
648d2d8e2d
This change introduces the hob support for both qemu platforms (virt and sbsa). As the hob list feature relies on transfer list, the transfer list support is promoted to common qemu build configuration. The platforms specific definitions are updated accordingly. Change-Id: I473d83388fe95408d34515bf7bcbdd64ce4e777d Signed-off-by: Kun Qin <kuqin@microsoft.com>
164 lines
4.3 KiB
Makefile
164 lines
4.3 KiB
Makefile
#
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# Copyright (c) 2023-2024, Linaro Limited and Contributors. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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include lib/libfdt/libfdt.mk
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include common/fdt_wrappers.mk
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PLAT_INCLUDES := -Iinclude/plat/arm/common/ \
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-I${PLAT_QEMU_COMMON_PATH}/ \
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-I${PLAT_QEMU_COMMON_PATH}/include \
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-I${PLAT_QEMU_PATH}/include \
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-Iinclude/common/tbbr
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ifeq (${ARCH},aarch32)
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QEMU_CPU_LIBS := lib/cpus/${ARCH}/cortex_a15.S
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else
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QEMU_CPU_LIBS := lib/cpus/aarch64/aem_generic.S \
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lib/cpus/aarch64/cortex_a53.S \
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lib/cpus/aarch64/cortex_a55.S \
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lib/cpus/aarch64/cortex_a57.S \
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lib/cpus/aarch64/cortex_a72.S \
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lib/cpus/aarch64/cortex_a76.S \
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lib/cpus/aarch64/cortex_a710.S \
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lib/cpus/aarch64/neoverse_n_common.S \
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lib/cpus/aarch64/neoverse_n1.S \
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lib/cpus/aarch64/neoverse_v1.S \
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lib/cpus/aarch64/neoverse_n2.S \
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lib/cpus/aarch64/qemu_max.S
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PLAT_INCLUDES += -Iinclude/plat/arm/common/${ARCH}
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endif
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PLAT_BL_COMMON_SOURCES := ${PLAT_QEMU_COMMON_PATH}/qemu_common.c \
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${PLAT_QEMU_COMMON_PATH}/qemu_console.c \
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drivers/arm/pl011/${ARCH}/pl011_console.S
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include lib/xlat_tables_v2/xlat_tables.mk
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PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS}
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ifneq ($(ENABLE_STACK_PROTECTOR), 0)
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PLAT_BL_COMMON_SOURCES += ${PLAT_QEMU_COMMON_PATH}/qemu_stack_protector.c
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endif
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BL1_SOURCES += drivers/io/io_semihosting.c \
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drivers/io/io_storage.c \
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drivers/io/io_fip.c \
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drivers/io/io_memmap.c \
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lib/semihosting/semihosting.c \
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lib/semihosting/${ARCH}/semihosting_call.S \
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${PLAT_QEMU_COMMON_PATH}/qemu_io_storage.c \
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${PLAT_QEMU_COMMON_PATH}/${ARCH}/plat_helpers.S \
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${PLAT_QEMU_COMMON_PATH}/qemu_bl1_setup.c \
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${QEMU_CPU_LIBS}
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BL2_SOURCES += drivers/io/io_semihosting.c \
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drivers/io/io_storage.c \
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drivers/io/io_fip.c \
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drivers/io/io_memmap.c \
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lib/semihosting/semihosting.c \
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lib/semihosting/${ARCH}/semihosting_call.S \
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${PLAT_QEMU_COMMON_PATH}/qemu_io_storage.c \
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${PLAT_QEMU_COMMON_PATH}/${ARCH}/plat_helpers.S \
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${PLAT_QEMU_COMMON_PATH}/qemu_bl2_setup.c \
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${PLAT_QEMU_COMMON_PATH}/qemu_bl2_mem_params_desc.c \
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${PLAT_QEMU_COMMON_PATH}/qemu_image_load.c \
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common/desc_image_load.c \
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common/fdt_fixup.c \
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${FDT_WRAPPERS_SOURCES}
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BL31_SOURCES += ${QEMU_CPU_LIBS} \
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lib/semihosting/semihosting.c \
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lib/semihosting/${ARCH}/semihosting_call.S \
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plat/common/plat_psci_common.c \
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${PLAT_QEMU_COMMON_PATH}/aarch64/plat_helpers.S \
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${PLAT_QEMU_COMMON_PATH}/qemu_bl31_setup.c \
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common/fdt_fixup.c \
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${QEMU_GIC_SOURCES}
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# CPU flag enablement
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ifeq (${ARCH},aarch64)
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# Cpu core architecture level:
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# v8.0: a53, a57, a72
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# v8.2: a55, a76, n1
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# v8.4: v1
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# v9.0: a710, n2
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#
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#
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# We go v8.0 by default and will enable all features we want
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ARM_ARCH_MAJOR ?= 8
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ARM_ARCH_MINOR ?= 0
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# 8.0
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ENABLE_FEAT_CSV2_2 := 2
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# 8.1
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ENABLE_FEAT_PAN := 2
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ENABLE_FEAT_VHE := 2
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# 8.2
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# TF-A currently does not permit dynamic detection of FEAT_RAS
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# so this is the only safe setting
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ENABLE_FEAT_RAS := 0
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# 8.4
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ENABLE_FEAT_SEL2 := 2
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ENABLE_FEAT_DIT := 2
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ENABLE_TRF_FOR_NS := 2
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# 8.5
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ENABLE_FEAT_RNG := 2
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# TF-A currently does not do dynamic detection of FEAT_SB.
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# Compiler puts SB instruction when it is enabled.
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ENABLE_FEAT_SB := 0
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# 8.6
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ENABLE_FEAT_ECV := 2
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ENABLE_FEAT_FGT := 2
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# 8.7
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ENABLE_FEAT_HCX := 2
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# SPM_MM is not compatible with ENABLE_SVE_FOR_NS (build breaks)
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ifeq (${SPM_MM},1)
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ENABLE_SVE_FOR_NS := 0
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ENABLE_SME_FOR_NS := 0
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else
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ENABLE_SVE_FOR_NS := 2
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ENABLE_SME_FOR_NS := 2
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endif
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ifeq (${ENABLE_RME},1)
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BL31_SOURCES += plat/qemu/common/qemu_plat_attest_token.c \
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plat/qemu/common/qemu_realm_attest_key.c
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endif
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# Treating this as a memory-constrained port for now
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USE_COHERENT_MEM := 0
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# This can be overridden depending on CPU(s) used in the QEMU image
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HW_ASSISTED_COHERENCY := 1
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CTX_INCLUDE_AARCH32_REGS := 0
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ifeq (${CTX_INCLUDE_AARCH32_REGS}, 1)
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$(error "This is an AArch64-only port; CTX_INCLUDE_AARCH32_REGS must be disabled")
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endif
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# Pointer Authentication sources
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ifeq ($(BRANCH_PROTECTION),$(filter $(BRANCH_PROTECTION),1 2 3))
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PLAT_BL_COMMON_SOURCES += plat/arm/common/aarch64/arm_pauth.c
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endif
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ifeq (${TRANSFER_LIST}, 1)
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include lib/transfer_list/transfer_list.mk
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endif
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ifeq (${HOB_LIST}, 1)
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include lib/hob/hob.mk
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endif
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endif
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