mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-05-03 17:38:39 +00:00
bdac600bc8
Older GNU binutils version require to specify at least "armv8.5-a" for the ARM architecture revision to accept "bti" instructions in the assembly code. Binutils v2.35 have relaxed this, since "bti" is in the hint space, so is ignored on older cores and does NOT require a BTI enabled core to execute. To not exclude those older binutils versions (as shipped with Ubuntu 20.04), use the "hint" encoding for the "bti" instructions, which are accepted regardless of the minimum architecture revision. Hide this encoding in a macro, to make the "bti" usage more readable in the source code. Change-Id: I005586efd8974a3f2c7202896c881bb5fed07eea Signed-off-by: Andre Przywara <andre.przywara@arm.com>
309 lines
8 KiB
ArmAsm
309 lines
8 KiB
ArmAsm
/*
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* Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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.globl flush_dcache_range
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.globl flush_dcache_to_popa_range
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.globl flush_dcache_to_popa_range_mte2
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.globl clean_dcache_range
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.globl inv_dcache_range
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.globl dcsw_op_louis
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.globl dcsw_op_all
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.globl dcsw_op_level1
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.globl dcsw_op_level2
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.globl dcsw_op_level3
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/* Opcodes for data cache maintenance by PA instructions. */
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/*
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* sys #6, c7, c14, #1, x0
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* DC CIPAPA, X0
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*/
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#define dc_cipapa_x0 0xd50e7e20
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/*
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* sys #6, c7, c14, #3, x0
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* DC CIDGPAPA, X0
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*/
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#define dc_cigdpapa_x0 0xd50e7ea0
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/*
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* This macro can be used for implementing various data cache operations `op`
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*/
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.macro do_dcache_maintenance_by_mva op
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/* Exit early if size is zero */
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cbz x1, exit_loop_\op
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dcache_line_size x2, x3
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add x1, x0, x1
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sub x3, x2, #1
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bic x0, x0, x3
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loop_\op:
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dc \op, x0
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add x0, x0, x2
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cmp x0, x1
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b.lo loop_\op
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dsb sy
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exit_loop_\op:
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ret
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.endm
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/* op: the hexadecimal instruction opcode for the cache operation */
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.macro do_dcache_maintenance_instr op
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/* Exit early if size is zero */
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cbz x1, exit_loop_\op
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dcache_line_size x2, x3
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sub x3, x2, #1
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bic x0, x0, x3
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add x1, x1, x0
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loop_\op:
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.inst \op
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add x0, x0, x2
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cmp x0, x1
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b.lo loop_\op
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dsb osh
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exit_loop_\op:
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ret
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.endm
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.macro check_plat_can_cmo
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#if CONDITIONAL_CMO
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mov x3, x30
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mov x2, x0
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bl plat_can_cmo
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mov x30, x3
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cbnz x0, 1f
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ret
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1:
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mov x0, x2
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#endif
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.endm
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/* -------------------------------------------
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* DCache Clean+Invalidate by MVA from base
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* address till size. 'x0' = addr, 'x1' = size
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* -------------------------------------------
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*/
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func flush_dcache_range
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check_plat_can_cmo
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do_dcache_maintenance_by_mva civac
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endfunc flush_dcache_range
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/* ------------------------------------------
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* DCache Clean by MVA from base address till
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* size. 'x0' = addr, 'x1' = size
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* ------------------------------------------
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*/
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func clean_dcache_range
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check_plat_can_cmo
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do_dcache_maintenance_by_mva cvac
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endfunc clean_dcache_range
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/* ------------------------------------------
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* DCache Invalidate by MVA from base address
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* till size. 'x0' = addr, 'x1' = size
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* ------------------------------------------
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*/
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func inv_dcache_range
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check_plat_can_cmo
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do_dcache_maintenance_by_mva ivac
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endfunc inv_dcache_range
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/*
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* ------------------------------------------
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* DCache Clean+Invalidate by PA to POPA from
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* base address till size.
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* 'x0' = addr, 'x1' = size
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* ------------------------------------------
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*/
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func flush_dcache_to_popa_range
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check_plat_can_cmo
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/* dc cipapa, x0 */
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do_dcache_maintenance_instr dc_cipapa_x0
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endfunc flush_dcache_to_popa_range
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/*
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* ------------------------------------------
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* Clean+Invalidate by PA to POPA (MTE2)
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* from base address till size.
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* 'x0' = addr, 'x1' = size
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* ------------------------------------------
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* On implementations with FEAT_MTE2, Root firmware must issue
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* DC_CIGDPAPA instead of DC_CIPAPA, in order to additionally
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* clean and invalidate Allocation Tags associated with the
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* affected locations.
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*/
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func flush_dcache_to_popa_range_mte2
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check_plat_can_cmo
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/* dc cigdpapa, x0 */
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do_dcache_maintenance_instr dc_cigdpapa_x0
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endfunc flush_dcache_to_popa_range_mte2
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/* ---------------------------------------------------------------
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* Data cache operations by set/way to the level specified
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*
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* The main function, do_dcsw_op requires:
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* x0: The operation type (0-2), as defined in arch.h
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* x3: The last cache level to operate on
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* x9: clidr_el1
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* x10: The cache level to begin operation from
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* and will carry out the operation on each data cache from level 0
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* to the level in x3 in sequence
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*
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* The dcsw_op macro sets up the x3 and x9 parameters based on
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* clidr_el1 cache information before invoking the main function
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* ---------------------------------------------------------------
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*/
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.macro dcsw_op shift, fw, ls
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mrs x9, clidr_el1
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ubfx x3, x9, \shift, \fw
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lsl x3, x3, \ls
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mov x10, xzr
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b do_dcsw_op
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.endm
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func do_dcsw_op
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cbz x3, exit
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mrs x12, ID_AA64MMFR2_EL1 // stash FEAT_CCIDX identifier in x12
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ubfx x12, x12, #ID_AA64MMFR2_EL1_CCIDX_SHIFT, #ID_AA64MMFR2_EL1_CCIDX_LENGTH
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adr x14, dcsw_loop_table // compute inner loop address
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add x14, x14, x0, lsl #5 // inner loop is 8x32-bit instructions
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#if ENABLE_BTI
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add x14, x14, x0, lsl #2 // inner loop is + "bti j" instruction
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#endif
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mov x0, x9
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mov w8, #1
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loop1:
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add x2, x10, x10, lsr #1 // work out 3x current cache level
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lsr x1, x0, x2 // extract cache type bits from clidr
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and x1, x1, #7 // mask the bits for current cache only
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cmp x1, #2 // see what cache we have at this level
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b.lo level_done // nothing to do if no cache or icache
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msr csselr_el1, x10 // select current cache level in csselr
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isb // isb to sych the new cssr&csidr
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mrs x1, ccsidr_el1 // read the new ccsidr
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and x2, x1, #7 // extract the length of the cache lines
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add x2, x2, #4 // add 4 (line length offset)
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cbz x12, 1f // check for FEAT_CCIDX for Associativity
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ubfx x4, x1, #3, #21 // x4 = associativity CCSIDR_EL1[23:3]
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b 2f
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1:
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ubfx x4, x1, #3, #10 // x4 = associativity CCSIDR_EL1[12:3]
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2:
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clz w5, w4 // bit position of way size increment
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lsl w9, w4, w5 // w9 = aligned max way number
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lsl w16, w8, w5 // w16 = way number loop decrement
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orr w9, w10, w9 // w9 = combine way and cache number
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cbz x12, 3f // check for FEAT_CCIDX for NumSets
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ubfx x6, x1, #32, #24 // x6 (w6) = numsets CCSIDR_EL1[55:32]
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// ISA will not allow x->w ubfx
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b 4f
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3:
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ubfx w6, w1, #13, #15 // w6 = numsets CCSIDR_EL1[27:13]
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4:
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lsl w17, w8, w2 // w17 = set number loop decrement
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dsb sy // barrier before we start this level
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br x14 // jump to DC operation specific loop
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.macro dcsw_loop _op
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#if ENABLE_BTI
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BTI j
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#endif
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loop2_\_op:
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lsl w7, w6, w2 // w7 = aligned max set number
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loop3_\_op:
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orr w11, w9, w7 // combine cache, way and set number
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dc \_op, x11
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subs w7, w7, w17 // decrement set number
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b.hs loop3_\_op
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subs x9, x9, x16 // decrement way number
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b.hs loop2_\_op
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b level_done
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.endm
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level_done:
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add x10, x10, #2 // increment cache number
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cmp x3, x10
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b.hi loop1
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msr csselr_el1, xzr // select cache level 0 in csselr
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dsb sy // barrier to complete final cache operation
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isb
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exit:
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ret
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endfunc do_dcsw_op
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dcsw_loop_table:
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dcsw_loop isw
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dcsw_loop cisw
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dcsw_loop csw
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func dcsw_op_louis
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check_plat_can_cmo
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dcsw_op #LOUIS_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT
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endfunc dcsw_op_louis
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func dcsw_op_all
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check_plat_can_cmo
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dcsw_op #LOC_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT
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endfunc dcsw_op_all
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/* ---------------------------------------------------------------
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* Helper macro for data cache operations by set/way for the
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* level specified
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* ---------------------------------------------------------------
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*/
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.macro dcsw_op_level level
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mrs x9, clidr_el1
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mov x3, \level
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sub x10, x3, #2
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b do_dcsw_op
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.endm
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/* ---------------------------------------------------------------
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* Data cache operations by set/way for level 1 cache
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*
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* The main function, do_dcsw_op requires:
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* x0: The operation type (0-2), as defined in arch.h
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* ---------------------------------------------------------------
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*/
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func dcsw_op_level1
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check_plat_can_cmo
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dcsw_op_level #(1 << LEVEL_SHIFT)
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endfunc dcsw_op_level1
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/* ---------------------------------------------------------------
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* Data cache operations by set/way for level 2 cache
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*
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* The main function, do_dcsw_op requires:
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* x0: The operation type (0-2), as defined in arch.h
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* ---------------------------------------------------------------
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*/
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func dcsw_op_level2
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check_plat_can_cmo
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dcsw_op_level #(2 << LEVEL_SHIFT)
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endfunc dcsw_op_level2
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/* ---------------------------------------------------------------
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* Data cache operations by set/way for level 3 cache
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*
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* The main function, do_dcsw_op requires:
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* x0: The operation type (0-2), as defined in arch.h
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* ---------------------------------------------------------------
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*/
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func dcsw_op_level3
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check_plat_can_cmo
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dcsw_op_level #(3 << LEVEL_SHIFT)
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endfunc dcsw_op_level3
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