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ef738d19d3
Currently, the calling core (meaning the core which received the call to CPU_ON or the powerdown path of CPU_SUSPEND on the same core) is in charge of initialising the context for the waking core (the warmboot entrypoint for both). This is convenient because the calling core can write the context while in coherency and the waking core will only need the context after its entered coherency. This avoids any cache maintenance and makes communication simple. However, this has 3 main problems: a) asymmetric feature support is problematic - the calling core has no way of knowing the feature set of the waking core. If the two diverge, the architectural feature discovery via ID registers breaks down. We've thus far "fixed" this on a case by case basis which doesn't scale and introduces redundancy. b) powerdown abandon (pabandon) introduces a contradiction - the calling core has to initialise the context for when the core wakes up, but should the core not powerdown it needs its old context intact. The only way to work around this is by keeping two copies of context which incurs a runtime and memory overhead. c) cm_prepare_el3_exit[_ns]() doesn't have access to the entrypoint but needs it to make initialisation decisions. We can infer some of this from registers that have already been written but this is awkwardly limiting for what we can do. This also necessitates the split from the context initialisation. We can solve all three by a making a core be in full ownership of its own context. The calling core then only writes entrypoint information and nothing else. The waking core then initialises its own context as it sees fit with full knowledge of the whole picture. The only tricky bit is cache coherency - the waking core has to be able to coherently observe its new entrypoint. Calling cores will write to the shared region with coherent caches on. If we make sure to read the context only after the waking core has entered coherency, then we can avoid cache operations and let hardware handle everything. We can skip the spsr check for FEAT_TCR2 as it doesn't make a difference. We can also skip enabling it twice from generic code. Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I86e7fe8b698191fc3b469e5ced1fd010f8754b0e
260 lines
7.6 KiB
C
260 lines
7.6 KiB
C
/*
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* Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CPU_DATA_H
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#define CPU_DATA_H
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#include <platform_def.h> /* CACHE_WRITEBACK_GRANULE required */
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#include <bl31/ehf.h>
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/* Size of psci_cpu_data structure */
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#define PSCI_CPU_DATA_SIZE 12
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#ifdef __aarch64__
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/* 8-bytes aligned size of psci_cpu_data structure */
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#define PSCI_CPU_DATA_SIZE_ALIGNED ((PSCI_CPU_DATA_SIZE + 7) & ~7)
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#if ENABLE_RME
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/* Size of cpu_context array */
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#define CPU_DATA_CONTEXT_NUM 3
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/* Offset of cpu_ops_ptr, size 8 bytes */
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#define CPU_DATA_CPU_OPS_PTR 0x20
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#else /* ENABLE_RME */
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#define CPU_DATA_CONTEXT_NUM 2
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#define CPU_DATA_CPU_OPS_PTR 0x18
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#endif /* ENABLE_RME */
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#if ENABLE_PAUTH
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/* 8-bytes aligned offset of apiakey[2], size 16 bytes */
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#define CPU_DATA_APIAKEY_OFFSET (0x8 + PSCI_CPU_DATA_SIZE_ALIGNED \
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+ CPU_DATA_CPU_OPS_PTR)
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#define CPU_DATA_CRASH_BUF_OFFSET (0x10 + CPU_DATA_APIAKEY_OFFSET)
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#else /* ENABLE_PAUTH */
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#define CPU_DATA_CRASH_BUF_OFFSET (0x8 + PSCI_CPU_DATA_SIZE_ALIGNED \
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+ CPU_DATA_CPU_OPS_PTR)
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#endif /* ENABLE_PAUTH */
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/* need enough space in crash buffer to save 8 registers */
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#define CPU_DATA_CRASH_BUF_SIZE 64
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#else /* !__aarch64__ */
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#if CRASH_REPORTING
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#error "Crash reporting is not supported in AArch32"
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#endif
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#define WARMBOOT_EP_INFO 0x0
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#define CPU_DATA_CPU_OPS_PTR 0x4
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#define CPU_DATA_CRASH_BUF_OFFSET (CPU_DATA_CPU_OPS_PTR + PSCI_CPU_DATA_SIZE)
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#endif /* __aarch64__ */
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#if CRASH_REPORTING
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#define CPU_DATA_CRASH_BUF_END (CPU_DATA_CRASH_BUF_OFFSET + \
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CPU_DATA_CRASH_BUF_SIZE)
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#else
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#define CPU_DATA_CRASH_BUF_END CPU_DATA_CRASH_BUF_OFFSET
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#endif
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/* buffer space for EHF data is sizeof(pe_exc_data_t) */
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#define CPU_DATA_EHF_DATA_SIZE 8
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#define CPU_DATA_EHF_DATA_BUF_OFFSET CPU_DATA_CRASH_BUF_END
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#if defined(IMAGE_BL31) && EL3_EXCEPTION_HANDLING
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#define CPU_DATA_EHF_DATA_BUF_END (CPU_DATA_EHF_DATA_BUF_OFFSET + \
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CPU_DATA_EHF_DATA_SIZE)
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#else
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#define CPU_DATA_EHF_DATA_BUF_END CPU_DATA_EHF_DATA_BUF_OFFSET
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#endif /* EL3_EXCEPTION_HANDLING */
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/* cpu_data size is the data size rounded up to the platform cache line size */
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#define CPU_DATA_SIZE (((CPU_DATA_EHF_DATA_BUF_END + \
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CACHE_WRITEBACK_GRANULE - 1) / \
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CACHE_WRITEBACK_GRANULE) * \
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CACHE_WRITEBACK_GRANULE)
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#if ENABLE_RUNTIME_INSTRUMENTATION
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/* Temporary space to store PMF timestamps from assembly code */
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#define CPU_DATA_PMF_TS_COUNT 1
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#if __aarch64__
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#define CPU_DATA_PMF_TS0_OFFSET CPU_DATA_EHF_DATA_BUF_END
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#else
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/* alignment */
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#define CPU_DATA_PMF_TS0_OFFSET (CPU_DATA_EHF_DATA_BUF_END + 8)
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#endif
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#define CPU_DATA_PMF_TS0_IDX 0
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#endif
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#ifndef __ASSEMBLER__
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#include <assert.h>
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#include <stdint.h>
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#include <arch_helpers.h>
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#include <lib/cassert.h>
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#include <lib/psci/psci.h>
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#include <platform_def.h>
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/* Offsets for the cpu_data structure */
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#define CPU_DATA_PSCI_LOCK_OFFSET __builtin_offsetof\
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(cpu_data_t, psci_svc_cpu_data.pcpu_bakery_info)
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#if PLAT_PCPU_DATA_SIZE
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#define CPU_DATA_PLAT_PCPU_OFFSET __builtin_offsetof\
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(cpu_data_t, platform_cpu_data)
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#endif
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typedef enum context_pas {
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CPU_CONTEXT_SECURE = 0,
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CPU_CONTEXT_NS,
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#if ENABLE_RME
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CPU_CONTEXT_REALM,
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#endif
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CPU_CONTEXT_NUM
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} context_pas_t;
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/*******************************************************************************
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* Function & variable prototypes
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******************************************************************************/
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/*******************************************************************************
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* Cache of frequently used per-cpu data:
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* Pointers to non-secure, realm, and secure security state contexts
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* Address of the crash stack
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* It is aligned to the cache line boundary to allow efficient concurrent
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* manipulation of these pointers on different cpus
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*
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* The data structure and the _cpu_data accessors should not be used directly
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* by components that have per-cpu members. The member access macros should be
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* used for this.
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******************************************************************************/
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typedef struct cpu_data {
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#ifdef __aarch64__
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void *cpu_context[CPU_DATA_CONTEXT_NUM];
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#endif /* __aarch64__ */
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entry_point_info_t *warmboot_ep_info;
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uintptr_t cpu_ops_ptr;
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struct psci_cpu_data psci_svc_cpu_data;
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#if ENABLE_PAUTH
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uint64_t apiakey[2];
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#endif
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#if CRASH_REPORTING
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u_register_t crash_buf[CPU_DATA_CRASH_BUF_SIZE >> 3];
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#endif
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#if ENABLE_RUNTIME_INSTRUMENTATION
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uint64_t cpu_data_pmf_ts[CPU_DATA_PMF_TS_COUNT];
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#endif
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#if PLAT_PCPU_DATA_SIZE
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uint8_t platform_cpu_data[PLAT_PCPU_DATA_SIZE];
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#endif
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#if defined(IMAGE_BL31) && EL3_EXCEPTION_HANDLING
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pe_exc_data_t ehf_data;
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#endif
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} __aligned(CACHE_WRITEBACK_GRANULE) cpu_data_t;
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extern cpu_data_t percpu_data[PLATFORM_CORE_COUNT];
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#ifdef __aarch64__
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CASSERT(CPU_DATA_CONTEXT_NUM == CPU_CONTEXT_NUM,
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assert_cpu_data_context_num_mismatch);
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#endif
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#if ENABLE_PAUTH
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CASSERT(CPU_DATA_APIAKEY_OFFSET == __builtin_offsetof
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(cpu_data_t, apiakey),
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assert_cpu_data_pauth_stack_offset_mismatch);
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#endif
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#if CRASH_REPORTING
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/* verify assembler offsets match data structures */
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CASSERT(CPU_DATA_CRASH_BUF_OFFSET == __builtin_offsetof
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(cpu_data_t, crash_buf),
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assert_cpu_data_crash_stack_offset_mismatch);
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#endif
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#if defined(IMAGE_BL31) && EL3_EXCEPTION_HANDLING
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CASSERT(CPU_DATA_EHF_DATA_BUF_OFFSET == __builtin_offsetof
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(cpu_data_t, ehf_data),
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assert_cpu_data_ehf_stack_offset_mismatch);
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#endif
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CASSERT(CPU_DATA_SIZE == sizeof(cpu_data_t),
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assert_cpu_data_size_mismatch);
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CASSERT(CPU_DATA_CPU_OPS_PTR == __builtin_offsetof
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(cpu_data_t, cpu_ops_ptr),
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assert_cpu_data_cpu_ops_ptr_offset_mismatch);
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#if ENABLE_RUNTIME_INSTRUMENTATION
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CASSERT(CPU_DATA_PMF_TS0_OFFSET == __builtin_offsetof
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(cpu_data_t, cpu_data_pmf_ts[0]),
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assert_cpu_data_pmf_ts0_offset_mismatch);
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#endif
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struct cpu_data *_cpu_data_by_index(uint32_t cpu_index);
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#ifdef __aarch64__
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/* Return the cpu_data structure for the current CPU. */
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static inline struct cpu_data *_cpu_data(void)
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{
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return (cpu_data_t *)read_tpidr_el3();
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}
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#else
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struct cpu_data *_cpu_data(void);
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#endif
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/*
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* Returns the index of the cpu_context array for the given security state.
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* All accesses to cpu_context should be through this helper to make sure
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* an access is not out-of-bounds. The function assumes security_state is
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* valid.
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*/
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static inline context_pas_t get_cpu_context_index(uint32_t security_state)
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{
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if (security_state == SECURE) {
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return CPU_CONTEXT_SECURE;
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} else {
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#if ENABLE_RME
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if (security_state == NON_SECURE) {
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return CPU_CONTEXT_NS;
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} else {
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assert(security_state == REALM);
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return CPU_CONTEXT_REALM;
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}
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#else
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assert(security_state == NON_SECURE);
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return CPU_CONTEXT_NS;
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#endif
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}
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}
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/**************************************************************************
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* APIs for initialising and accessing per-cpu data
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*************************************************************************/
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void init_cpu_ops(void);
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#define get_cpu_data(_m) _cpu_data()->_m
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#define set_cpu_data(_m, _v) _cpu_data()->_m = (_v)
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#define get_cpu_data_by_index(_ix, _m) _cpu_data_by_index(_ix)->_m
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#define set_cpu_data_by_index(_ix, _m, _v) _cpu_data_by_index(_ix)->_m = (_v)
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/* ((cpu_data_t *)0)->_m is a dummy to get the sizeof the struct member _m */
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#define flush_cpu_data(_m) flush_dcache_range((uintptr_t) \
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&(_cpu_data()->_m), \
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sizeof(((cpu_data_t *)0)->_m))
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#define inv_cpu_data(_m) inv_dcache_range((uintptr_t) \
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&(_cpu_data()->_m), \
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sizeof(((cpu_data_t *)0)->_m))
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#define flush_cpu_data_by_index(_ix, _m) \
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flush_dcache_range((uintptr_t) \
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&(_cpu_data_by_index(_ix)->_m), \
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sizeof(((cpu_data_t *)0)->_m))
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#endif /* __ASSEMBLER__ */
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#endif /* CPU_DATA_H */
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