/*
 * Copyright (c) 2019-2025, Arm Limited. All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

#include <common/tbbr/tbbr_img_def.h>
#include <platform_def.h>

/* DTB load addresses */
#define TB_SOC_FW_ADDR	(ARM_BL_RAM_BASE + 0x300)
#define TOS_FW_ADDR	(ARM_BL_RAM_BASE + 0x500)

/dts-v1/;

/ {
	dtb-registry {
		compatible = "fconf,dyn_cfg-dtb_registry";

		tb_fw-config {
			load-address = <0x0 TB_SOC_FW_ADDR>;
			max-size = <0x1800>;
			id = <TB_FW_CONFIG_ID>;
		};

		hw-config {
			load-address = <0x0 0x07f00000>;
			max-size = <PLAT_ARM_HW_CONFIG_SIZE>;
			id = <HW_CONFIG_ID>;
			secondary-load-address = <0x0 0x82000000>;
		};

		/*
		 * Load SoC and TOS firmware configs at the base of
		 * non shared SRAM. The runtime checks ensure we don't
		 * overlap BL2, BL31 or BL32. The NT firmware config
		 * is loaded at base of DRAM.
		 */
		soc_fw-config {
			load-address = <0x0 TB_SOC_FW_ADDR>;
			max-size = <0x200>;
			id = <SOC_FW_CONFIG_ID>;
		};

/* If required, SPD should enable loading of trusted OS fw config */
#if defined(SPD_tspd) || defined(SPD_spmd)
		tos_fw-config {
			load-address = <0x0 TOS_FW_ADDR>;
#if ENABLE_RME
			secondary-load-address = <0x0 0x7e00000>;
#endif /* ENABLE_RME */
			max-size = <0xB00>;
			id = <TOS_FW_CONFIG_ID>;
		};
#endif
		nt_fw-config {
			load-address = <0x0 0x80000000>;
			max-size = <0x200>;
			id = <NT_FW_CONFIG_ID>;
		};
	};
};