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3 commits

Author SHA1 Message Date
Jit Loon Lim
9b8d813cc9 feat(intel): reset manager support for Agilex5 SoC FPGA 
This patch is used to enable reset manager support
for Agilex5 SoC FPGA.
	1. Added HPS bridges support
		a. SOC2FPGA
		b. LWSOC2FPGA
		c. F2SDRAM
		d. F2SOC
	2. Added EMULATOR support
	3. Added WDT support
	4. Updated product name -> Agilex5
	5. Added SMP support

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Icab15b25f787fdccce1de75d102604db23beaf11
 2023-07-05 09:08:31 +08:00
Ang Tien Sung
9ce82519c6 feat(intel): fix bridge disable and reset 
Fix bridge sideband manager register clear and set incorrect
implementation. To support non-graceful full bridge disable
and enable.

Signed-off-by: Ang Tien Sung <tien.sung.ang@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I651f3ec163d954e8efb0542ec33bce96e51992db
 2023-04-11 00:17:00 +08:00
Sieu Mun Tang
11f4f03043 feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge 
This adds F2S and S2F bridge enable, disable and reset
sequence to enable, disable and reset properly the bridges
in SMC call or during reset.

The reset is also maskable as the SMC from uboot can
pass in the bridge mask when requesting for bridge
enable or disable.

Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ie144518c591664ef880016c9b3706968411bbf21
 2022-05-05 22:58:03 +08:00