TF-A BL2 always boot at 650MHz using an algorithm to calculate PLL1
settings, without reading DT. Remove the corresponding nodes.
Change-Id: I0003337d8d37df7b2a70a84b5475f4278c4c4669
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
LSI was too slow to provide enough random numbers (limited
to 6ms for 16 bytes production). Switch to CSI that allow
to get the RNG fifo ready in less than 50µs.
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Change-Id: I76d1fe58e2f4d5416a96f48123ae36bd82d8a8ee
For peripheral where both status and secure-status are set to okay,
the function fdt_get_status() returns the same status (DT_SHARED) if
secure-status property is omitted. This secure-status property can then
be removed in boards DT files for iwdg nodes.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I9f9360842d4d41288db0cf1b92063f347c72d137
The RCC security is managed with a dedicated compatible:
"st,stm32mp1-rcc-secure" [1].
Remove useless secure-status property in boards rcc nodes.
[1] 812daf916c ("feat(st): update the security based on new compatible")
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Iff31044ade78dd9c432120dce65375fe2b0d36d6
With recent changes, TF-A now panics on MC-1, Avenger96 and Odyssey:
NOTICE: CPU: STM32MP157C?? Rev.B
NOTICE: Model: Linux Automation MC-1 board
ERROR: regul ldo3: max value 750 is invalid
PANIC at PC : 0x2ffeebb7
as the driver takes great offense at the content of the device
tree. The parts in question were copy-pasted from ST DTs, but
those ST DTs were fixed by commit 67d95409ba
("refactor(stm32mp1-fdts): update regulator description").
Fix the breakage by transplanting the same changes into all
remaining STM32MP1 DTs.
Change was boot-tested on MC-1, but only build tested for the
other two.
Fixes: bba9fdee58 ("feat(stm32mp1): add regulator framework compilation")
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Change-Id: I143d0091625f62c313b3b71449c9ad99583d01c8
There is one dtsi file per SoC version:
- STM32MP151: common part for all version, Single Cortex-A7
- STM32MP153: Dual Cortex-A7
- STM32MP157: + GPU and DSI, but not needed for TF-A
The STM32MP15xC include a cryptography peripheral, add it in a dedicated
file.
There are 4 packages available, for which the IOs number change. Have one
file for each package. The 2 packages AB and AD are added.
STM32157A-DK1 and STM32MP157C-DK2 share most of their features, a common
dkx file is then created.
Some reordering is done in other files, and realign with kernel DT files.
The DDR files are generated with our internal tool, no changes in the
registers values.
Change-Id: I9f2ef00306310abe34b94c2f10fc7a77a10493d1
Signed-off-by: Yann Gautier <yann.gautier@st.com>
LTDC modifies the clock frequency to adapt it to the display. Such
frequency change is not detected by the FDCAN driver that instead
caches the value at probe and pretends to use it later.
This change fixes the issue by moving the FDCAN to PLL4_R,
leaving the LTDC alone on PLL4_Q.
Signed-off-by: Antonio Borneo <antonio.borneo@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I8230868b2b5fd6deb6e3f9dc3911030d8d484c58
Add board support for Avenger96 board from Arrow Electronics. This
board is based on STM32MP157A SoC and is one of the 96Boards Consumer
Edition platform.
More information about this board can be found in 96Boards website:
https://www.96boards.org/product/avenger96/
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Change-Id: Ic905f26c38d03883c6e4ea221b4b275a4b534857
