4 commits

Author	SHA1	Message	Date
Jacky Bai	e00fe11df3	fix(imx8m): add ddr4 dvfs sw workaround for ERR050712 ... APB Write data corruption following MRCTRL0.mr_wr=1 while hardware-driven MR access is occurring When performing a software driven MR access, the following sequence must be done automatically before performing other APB register accesses: 1. Set MRCTRL0.mr_wr=1 2. Check for MRSTAT.mr_wr_busy=0. If not, go to step (2) 3. Check for MRSTAT.mr_wr_busy=0 again (for the second time), if not, go to step (2). Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Change-Id: Ie26e08bcc83d3ed4844ed04a853162308dcdccd0	2023-02-28 14:27:28 +08:00
Jacky Bai	0e39488ff3	feat(imx8m): update the ddr4 dvfs flow to include ddr3l support ... the DDR3L & DDR4 can share same piece of code for DDR frequency scaling. So update the ddr4 dvfs flow to support DDR3L too. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Anson Huang <anson.huang@nxp.com> Change-Id: Ifc6981f05ed8a4e399adad97690197a9680f554d	2023-02-27 11:22:51 +08:00
Jacky Bai	093888caaf	feat(imx8m): fix the ddr4 dvfs random hang on imx8m ... Remove the while loop waiting in step12 to align with what we did before, just use a 'if' condition check for debug purpose. Tested-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: Id2685c5f628270a24944470d675a5c8706f39f13	2023-02-27 11:20:23 +08:00
Jacky Bai	9c336f6118	feat(imx8m): add the ddr frequency change support for imx8m family ... Add the DDR frequency change support. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: If1167785796b8678c351569b83d2922c66f6e530	2022-06-27 09:27:11 +08:00