Commit graph

8 commits

Author SHA1 Message Date
Jay Buddhabhatti
ade92a64e4 feat(xilinx): add handler for power down req sgi irq
On receiving CPU power down callback, TF-A raises SGI interrupt to all active
cores to power down each active cores. Add handler for this SGI IRQ.

By default TF-A uses SGI 6 for CPU power down request. This can be
configurable through CPU_PWRDWN_SGI build flag.

e.g., If user wants to use SGI 7 instead of SGI 6 then provide build
flag CPU_PWRDWN_SGI=7

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: Id0df32187d1de3f0af4486eb4d4930cb3ab01dbd
2024-01-09 04:15:27 -08:00
Jay Buddhabhatti
3dd118cf9d feat(xilinx): add wrapper to handle cpu power down req
Firmware sends CPU power down request to TF-A through NOTIFY_CB
callback. It indicates CPU needs to power down.

Add wrapper to handle CPU power down request from firmware
through IPI callback.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: Ic4aff874dd29da057c5ffde1899c7f0e5cdf6733
2024-01-09 00:38:21 -08:00
Jay Buddhabhatti
cebb7cc110 fix(versal-net): add redundant call to avoid glitches
Add redundant macro call to increase security by making
code glitch immune as security operations might be
called with the IPI command.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I84d84cca258b7cd981f62816c51032341e19095c
2023-08-08 12:52:05 +02:00
Jay Buddhabhatti
e8efb65afb fix(versal-net): change flag to increase security
Currently security flag is set to SECURE by default and
is changed to NON_SECURE if NS system is detected. In this
case NS system may access secure system if condition check
gets skipped due to glitches.

So, initialize security_flag to NON_SECURE_FLAG and switch
to SECURE_FLAG if the TrustZone bit is detected to be
in more secure state.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I7af54465bd8744ba97a58c02607631ee23619d47
2023-08-08 12:51:17 +02:00
Prasad Kummari
01a326abeb chore(xilinx): reorder include files as per TF-A guidelines
This commit reorders the include files in accordance with the
guidelines provided by Trusted Firmware-A (TF-A).
The include files are rearranged to ensure a consistent and
organized structure in the codebase, facilitating better
readability and maintainability.

https: //trustedfirmware-a.readthedocs.io/en/latest/process/coding-style.html#headers-and-inclusion
https://git.trustedfirmware.org/ci/tf-a-ci-scripts.git/tree/script/static-checks/

For example, to run header check:
/tf-a-ci-scripts/script/static-checks/check-include-order.py --tree ${PWD} > Includefileorder.txt

Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: Ia5802722e69859596b94f31ec40755adbf7d865b
2023-06-27 10:14:09 +05:30
Prasad Kummari
de7ed953e3 chore(xilinx): follow kernel doc format for functional documentation
For TF-A, there is no format specified for functional documentation.
For AMD-Xilinx platforms, following kernel-doc format for the functional
documentation to make sure AMD-xilinx documentation is align with
actual code.

For example use kernel-doc from linux to call:
<linux>/scripts/kernel-doc -man -v 1 >/dev/null file...

Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: Idcc9def408b6c8da35b36f67ef82fc00890e998c
2023-06-23 08:07:13 +01:00
Jay Buddhabhatti
964e55928c fix(xilinx): fix misra defects
This patch fixes defects 5.5, 10.1, 10.3, 10.4, 10.7 reported
by MISRA-2012 scan.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: Ie6f6e9bf2ce1335bbb61aa2e69a3a196865fd504
2023-03-27 23:09:00 -07:00
Jay Buddhabhatti
a92681d926 refactor(xilinx): move versal files to common place
Moved necessary files to common place so that it can be used for
Versal NET.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I611fa849207b082e6599acfb65c55d27b9c99435
2023-03-27 22:57:00 -07:00
Renamed from plat/xilinx/versal/pm_service/pm_svc_main.c (Browse further)