3 commits

Author	SHA1	Message	Date
Jimmy Huang	6b0d97b24a	cortex_a53: Add A53 errata #826319, #836870 ... - Apply a53 errata #826319 to revision <= r0p2 - Apply a53 errata #836870 to revision <= r0p3 - Update docs/cpu-specific-build-macros.md for newly added errata build flags Change-Id: I44918e36b47dca1fa29695b68700ff9bf888865e Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>	2015-08-05 19:58:39 +08:00
Soby Mathew	d3f70af6e0	Add CPU specific crash reporting handlers ... This patch adds handlers for dumping Cortex-A57 and Cortex-A53 specific register state to the CPU specific operations framework. The contents of CPUECTLR_EL1 are dumped currently. Change-Id: I63d3dbfc4ac52fef5e25a8cf6b937c6f0975c8ab	2014-08-20 19:14:31 +01:00
Soby Mathew	add403514d	Add CPU specific power management operations ... This patch adds CPU core and cluster power down sequences to the CPU specific operations framework introduced in a earlier patch. Cortex-A53, Cortex-A57 and generic AEM sequences have been added. The latter is suitable for the Foundation and Base AEM FVPs. A pointer to each CPU's operations structure is saved in the per-cpu data so that it can be easily accessed during power down seqeunces. An optional platform API has been introduced to allow a platform to disable the Accelerator Coherency Port (ACP) during a cluster power down sequence. The weak definition of this function (plat_disable_acp()) does not take any action. It should be overriden with a strong definition if the ACP is present on a platform. Change-Id: I8d09bd40d2f528a28d2d3f19b77101178778685d	2014-08-20 19:14:31 +01:00