Currently SGI interrupts are not received in secondary cores because
of issue in GIC configuration. In current Versal NET specific GIC
functions, redistributor configuration is not happening properly.
Because of that SGI interrupt from one processor to another processor
is not transferring. So, use common GIC handlers which will iterate
over all GIC redistributor frames and discovers per cpu redistributor
frame. Also, it initializes corresponding interface in GICv3.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I1433260b8520d6a315fdf5df86bd0688f92d211a
The commit 6bb49c876c ("style(hooks): adds Arm copyright style fix")
is enforcing proper case for ARM. That's why fix it in plat/xilinx to
make sure that pre-commit.copyright won't be touching platform specific
files.
Change-Id: I49c66e18d46ed871a6aa128c9b2a403d0cf83416
Signed-off-by: Michal Simek <michal.simek@amd.com>
Moved pm_defs.h file to common place so that it can be used for
Versal NET and ZynqMP. Also moved common code from zynqmp_pm_defs.h to
common place.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I2ee1e72258c6052cdd6467cdbcf4009afb98da49
The purpose of this code is to extract api_id from smc_fid but this masking
is done already in the code with using generic mask from smccc.h
(FUNCID_NUM_MASK). That's why remove FUNCID_MASK is which not needed and
actually also equal to already used FUNCID_NUM_MASK.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I1113825baa5d9d58d9d7c5d9d5855fecf62e8d45
Add SMP support for Versal NET via register access.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Akshay Belsare <Akshay.Belsare@amd.com>
Change-Id: I46d73e2cd678ae720b5255722b6b0611c22659e8
New SoC is a78 based with gicv3 and uart over pl011. Communication
interfaces are similar to Versal platform. System starts with Xilinx PLM
firmware which loads TF-A(bl31) to DDR, which is already configured, and
jumps to it. PLM also prepare handoff structure for TF-A with information
what components were load and flags which indicate which EL level SW should
be started.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Akshay Belsare <Akshay.Belsare@amd.com>
Change-Id: I2a16c242a77be6c91be3d198727dc3b9bbb97410
