4 commits

Author	SHA1	Message	Date
Sandrine Bailleux (on vacation)	5551264910	Merge changes I548e3034,I65c7fd1b,I1cdacc0f,If9ac35af into integration ... * changes: feat(intel): support QSPI ECC Linux for Agilex feat(intel): support QSPI ECC Linux for N5X feat(intel): support QSPI ECC Linux for Stratix10 feat(intel): add in QSPI ECC for Linux	2023-12-27 11:21:09 +01:00
Jit Loon Lim	4d122e5f19	feat(intel): add in QSPI ECC for Linux ... Add QSPI ECC new opcodes for Linux to access to SDM register Change-Id: If9ac35afdddb91db6bad6b474060cd001f6d89e6 Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>	2023-12-22 00:39:55 +08:00
Sieu Mun Tang	b727664e0d	fix(intel): add HPS remapper to remap base address for SDM ... Remap base address for SDM to access DRAM. Change-Id: If064bd1ff4571d3217b136d9b5ebbfdecb68231e Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>	2023-12-22 00:26:42 +08:00
Jit Loon Lim	7618403110	feat(intel): system manager support for Agilex5 SoC FPGA ... This patch is used to implement system manager data support for Agilex5 SoC FPGA. 1. Initial SM bring up 2. Support Candence SDMMC/NAND/COMBO PHY 3. Updated product name -> Agilex5 4. Updated register address based on y22ww52.2 RTL Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com> Change-Id: I12712bddfb67e36a2bf56d2d98ea4ca3037f0a82	2023-07-05 09:08:27 +08:00