In sunxi_soc_fdt_fixup(), we check for the value of "ret" again, after
calling fdt_node_offset_by_phandle(), even though the error value of
that lands in "node".
Check for "node" being non-negative instead, to properly detect any
errors here.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: I57c1406388dbe11d343038da173019519e18af3e
The Allwinner H616 and its siblings come in different die revisions,
some have 256 KB of L2 cache, some have 1 MB. This prevents a single
static cache description in the devicetree.
Use the cache size ID register (CCSIDR_EL1) to query the topology of the
L2 cache, and adjust the cache-sets and cache-size properties in the L2
cache DT node accordingly.
The ARM ARM does not promise (anymore) that the cache size can be derived
*architecturally* from this register, but the reading is definitely
correct for the Arm Cortex-A53 core used.
Change-Id: Id7dc324d783b8319fe5df6164be2f941d4cac82d
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
On at least one new device we see an Allwinner H700 SoC paired with the
X-Powers AXP717 PMIC. In contrast to the small AXP313, this is a quite
complete PMIC, with many voltage rails, battery and USB-C charging
support. It supports both RSB and I2C control options.
Add the compatible string to the list of checked devices. The AXP717
apparently does not feature a version ID register, but we read 0xff from
that address 0x3, so use this as an indication of its presence, since
this value differs from what we read from the other PMICs.
The register offset and bit position for the power off functionality is
again different, but easy to put into our switch/case.
Setting up regulators in TF-A is now somewhat obsolete, since U-Boot
does a much better job in this now, and can figure out which regulators
are actually needed. So we don't add the regulator setup code, and just
use the PMIC for the power-off functionality.
Change-Id: Ie6b4c91517014adcc79d9a3459c75545fa3a63e6
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Many newer boards with the H616 and its sibling H618 are now paired
with the X-Powers AXP313 PMIC. This is a simpler PMIC, with only a few
voltage rails and no extra functionality except the power key support.
In contrast to the AXP305 it can only be controlled via I2C.
Add a check to look for the AXP313 compatible string in the devicetree,
and set the PMIC type and I2C address accordingly, if one is found.
With only very few voltage rails available, all of them are mostly in
use and are thus enabled at reset already, so we can skip the regulator
setup entirely.
Change-Id: I01962854109e43793b4f56553c1ca9e1f752e30d
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The X-Powers AXP305 PMIC can be controlled via both I2C or RSB (an
Allwinner specific bus similar to I2C), but we chose to use only RSB,
because that's easier to program and also used by Linux. The AXP313a
PMIC however supports only I2C, so we need to support both buses, and
need to decide which to use at runtime.
Prepare the PMIC code to add (back) I2C support. We initially used I2C
on the H6/AXP805 combination, but replaced that later with RSB. So this
patch is bringing some of that older code back.
The decision whether to use I2C or RSB is made by the devicetree, since
on some boards even RSB capable PMICs are controlled via I2C, since they
share the bus with only I2C capable devices, for instance RTCs.
At the moment this will still use RSB to drive the AXP305, but the
(dynamic) I2C code will be used shortly to support the AXP313.
This increases the code size by one 4K page, but with 80K out of the
reserved 256K we are still very far away from our limit.
Change-Id: I65c1e7df93dbd2dcd171b3fc486533a2948cc75b
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Most devices based on Allwinner SoCs come with a certain fixed
combination of Power Management ICs (PMICs) and SoC, for instance the
A64 with the AXP803, or the H6 with the AXP805. This allowed us to
include the respective PMIC support code into each build target at build
time.
Similarly on H616 devices we initially saw only the AXP305, but for a
while now the simpler (and cheaper) AXP313a is a popular companion to
the H616 on many new boards. On at least one new device the AXP717 is
used as well.
With some rudimentary AXP version check in place we at least detected
the case of an unsupported SoC, but threw an error message, and lost
support for powering off the device.
Refactor the existing PMIC code to be able to support more than one
PMIC model, detected at runtime. For this we use a variable for the RSB
runtime address instead of hardcoding the address used on the AXP305,
and read the hardware bus address from the devicetree.
Also we look up the used PMIC in the devicetree, and set the PMIC model
accordingly. To be on the safe side, we also confirm the real PMIC used
by checking its version register and comparing that with the expected
value. Finally the register offset and value to power off the PMIC is
moved direclty into the platform code, as those values differ between
the different PMICs.
This is just refactoring and better error report, we still only support
the AXP305 on RSB at the moment.
Change-Id: I00b26ce4d30bb570ee1cd4979d0cdc9d6c020729
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Allwinner provides a number of SoCs that use the same die as the H616.
Some of those chips apparently use a slight variation of that die, that
differs in the way the CPU cores' power and reset controls are handled.
This die variation can be detected by reading the SRAM version register.
Provide a predicate function that returns false if that die variant is
used. Since the CPU power control code is shared for all supported SoCs,
we provide an instance of this function for each SoC, as a static
inline, and return true on all other SoCs. This allows to always use
this function, and still let the compiler optimise away the unneeded
branch for those older SoCs.
This function is unused for now, but is needed in the next patch.
Change-Id: I49e014b895b7e2f55b4e7dc2b3d8aa31cee711b5
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The die used in several variants of the Allwinner H616 SoC (H313, T507)
seems to produced in at least two revisions. The newer one differs from
the original by using a different CPU control register IP block.
Add those newly used register offsets to the respective header file. The
MMIO block itself is actually present in both variants, though the
registers are different. The new registers tend to use one register per
core, in contrast to one register per cluster in the older revisions.
Change-Id: Ifbda1bdc67a6a16fbb901dbc83996e4a148b7602
Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The header files describing the CPU cluster configuration IP block for
the H6 and H616 are actually identical, so merge them into one file and
move that to a common location. There is an upcoming SoC which will
similarly share a header file with the R329 SoC, so move that to the
same location already. In Allwinner's BSP source those two SoC groups
are typically called "NCAT" and "NCAT2", so use those names for the
shared header files. No functional change.
Change-Id: I98318373577344dbe228a81fa331ce660df32b5f
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
When using SCPI as the PSCI backend, firmware can wake up the CPUs and
cluster from sleep, so CPU idle states are available for the rich OS to
use. In that case, advertise them to the rich OS via the DTB.
Change-Id: I718ef6ef41212fe5213b11b4799613adbbe6e0eb
Signed-off-by: Samuel Holland <samuel@sholland.org>
So far the H616 was the only Allwinner SoC needed to amend the DTB, to
reserve the DRAM portion that BL31 occupies.
To allow other SoCs to modify the DTB as well, without duplicating code,
move the DTB change routines into Allwinner common code, and generalise
the current code to allow other modifications.
No functional change intended.
Change-Id: I080ea07b6470367f3c2573a4368f8ef5196d411c
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
In newer Allwiner SoCs, the AA64nAA32 wires are mapped to a new register
called "General Control Register0" in the manual rather than the
"Cluster 0 Control Register0" in older SoCs.
Now the position of AA64nAA32 (reg and bit offset) is defined in a few
macros instead assumed to be at bit offset 24 of
SUNXI_CPUCFG_CLS_CTRL_REG0.
Change-Id: I933d00b9a914bf7103e3a9dadbc6d7be1a409668
Signed-off-by: Icenowy Zheng <icenowy@sipeed.com>
When the BL31 for the Allwinner H616 runs in DRAM, we need to make sure
we tell the non-secure world about the memory region it uses.
Add a reserved-memory node to the DT, which covers the area that BL31
could occupy. The "no-map" property will prevent OSes from mapping
the area, so there would be no speculative accesses.
Change-Id: I808f3e1a8089da53bbe4fc6435a808e9159831e1
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The new Allwinner H616 SoC lacks the management controller and the secure
SRAM A2, so we need to tweak the memory map quite substantially:
We run BL31 in DRAM. Since the DRAM starts at 1GB, we cannot use our
compressed virtual address space (max 256MB) anymore, so we revert to
the full 32bit VA space and use a flat mapping throughout all of it.
The missing controller also means we need to always use the native PSCI
ops, using the CPUIDLE hardware, as SCPI and suspend depend on the ARISC.
Change-Id: I77169b452cb7f5dc2ef734f3fc6e5d931749141d
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
