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2 commits

Author SHA1 Message Date
Girisha Dengi
a773f4121b fix(intel): update nand driver to match GHRD design 
Update nand driver to match GHRD design, fix row
address calculation method and other misc updates.

Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I1cb3dda43e767ba243fbe89bfa18818db321c5c2
 2024-01-23 00:05:11 +08:00
Jit Loon Lim
ddaf02d171 feat(intel): sdmmc/nand/combo-phy/qspi driver for Agilex5 SoC FPGA 
This patch is used to implement sdmmc/nand/combo-phy
driver to support Cadence IP for Agilex5 SoC FPGA.
	1. Added SDMMC/NAND/COMBO-PHY support.
	2. Updated product name -> Agilex5
	3. Updated QSPI base address

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I6db689d2b784c9f59a25701ab34517f6f6b0a0e6
 2023-07-05 10:11:11 +08:00