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Author SHA1 Message Date
Jit Loon Lim
ddaf02d171 feat(intel): sdmmc/nand/combo-phy/qspi driver for Agilex5 SoC FPGA 
This patch is used to implement sdmmc/nand/combo-phy
driver to support Cadence IP for Agilex5 SoC FPGA.
	1. Added SDMMC/NAND/COMBO-PHY support.
	2. Updated product name -> Agilex5
	3. Updated QSPI base address

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I6db689d2b784c9f59a25701ab34517f6f6b0a0e6
 2023-07-05 10:11:11 +08:00