2 commits

Author	SHA1	Message	Date
Tien Hock Loh	811af8b768	plat: intel: Additional instruction required to enable global timer ... There are additional instruction needed to enable the global timer. This fixes the global timer initialization Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com> Change-Id: Idaf2d23359aacc417e2b7d8cdf1688b5cd17ca98	2020-06-08 22:03:54 +00:00
Hadi Asyrafi	d8820789ca	intel: Platform common code refactor ... Pull out common code from agilex and stratix10 Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Iddc0a9e6eccb30823d7b15615d5ce9c6bedb2abc	2019-08-01 16:39:27 +08:00

Renamed from plat/intel/soc/agilex/socfpga_delay_timer.c (Browse further)