From ffdf5ea47a5ffede59f6fc7bf32775598dcd75a0 Mon Sep 17 00:00:00 2001 From: Rajasekaran Kalidoss Date: Tue, 9 May 2023 12:28:07 +0200 Subject: [PATCH] docs(ethos-n): update build-options.rst Move documentation related to Arm(R) Ethos(TM)-N NPU driver from docs/plat/arm/arm-build-options.rst to docs/getting_started/build-options.rst. Signed-off-by: Rajasekaran Kalidoss Change-Id: I388e8dcd3950b11bc3305f5e6396ee2e49c04493 --- docs/getting_started/build-options.rst | 14 ++++++++++++++ docs/plat/arm/arm-build-options.rst | 14 -------------- docs/porting-guide.rst | 16 ++++++++-------- 3 files changed, 22 insertions(+), 22 deletions(-) diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst index c410a8e95..953a92e36 100644 --- a/docs/getting_started/build-options.rst +++ b/docs/getting_started/build-options.rst @@ -519,6 +519,20 @@ Common build options Firmware as error. It can take the value 1 (flag the use of deprecated APIs as error) or 0. The default is 0. +- ``ETHOSN_NPU_DRIVER``: boolean option to enable a SiP service that can + configure an Arm® Ethos™-N NPU. To use this service the target platform's + ``HW_CONFIG`` must include the device tree nodes for the NPU. Currently, only + the Arm Juno platform has this included in its ``HW_CONFIG`` and the platform + only loads the ``HW_CONFIG`` in AArch64 builds. Default is 0. + +- ``ETHOSN_NPU_TZMP1``: boolean option to enable TZMP1 support for the + Arm® Ethos™-N NPU. Requires ``ETHOSN_NPU_DRIVER`` and + ``TRUSTED_BOARD_BOOT`` to be enabled. + +- ``ETHOSN_NPU_FW``: location of the NPU firmware binary + (```ethosn.bin```). This firmware image will be included in the FIP and + loaded at runtime. + - ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions targeted at EL3. When set ``0`` (default), no exceptions are expected or handled at EL3, and a panic will result. The exception to this rule is when diff --git a/docs/plat/arm/arm-build-options.rst b/docs/plat/arm/arm-build-options.rst index 317926760..e81052b36 100644 --- a/docs/plat/arm/arm-build-options.rst +++ b/docs/plat/arm/arm-build-options.rst @@ -95,20 +95,6 @@ Arm Platform Build Options platforms. If this option is specified, then the path to the CryptoCell SBROM library must be specified via ``CCSBROM_LIB_PATH`` flag. -- ``ARM_ETHOSN_NPU_DRIVER``: boolean option to enable a SiP service that can - configure an Arm® Ethos™-N NPU. To use this service the target platform's - ``HW_CONFIG`` must include the device tree nodes for the NPU. Currently, only - the Arm Juno platform has this included in its ``HW_CONFIG`` and the platform - only loads the ``HW_CONFIG`` in AArch64 builds. Default is 0. - -- ``ARM_ETHOSN_NPU_TZMP1``: boolean option to enable TZMP1 support for the - Arm® Ethos™-N NPU. Requires ``ARM_ETHOSN_NPU_DRIVER`` and - ``TRUSTED_BOARD_BOOT`` to be enabled. - -- ``ARM_ETHOSN_NPU_FW``: location of the NPU firmware binary - (```ethosn.bin```). This firmware image will be included in the FIP and - loaded at runtime. - - ``ARM_GPT_SUPPORT``: Enable GPT parser to get the entry address and length of the various partitions present in the GPT image. This support is available only for the BL2 component, and it is disabled by default. diff --git a/docs/porting-guide.rst b/docs/porting-guide.rst index f07402189..5a017ce0f 100644 --- a/docs/porting-guide.rst +++ b/docs/porting-guide.rst @@ -591,32 +591,32 @@ configuration must be performed: If the platform port uses the Arm® Ethos™-N NPU driver with TZMP1 support enabled, the following constants and configuration must also be defined: -- **ARM_ETHOSN_NPU_PROT_FW_NSAID** +- **ETHOSN_NPU_PROT_FW_NSAID** Defines the Non-secure Access IDentity (NSAID) that the NPU shall use to access the protected memory that contains the NPU's firmware. -- **ARM_ETHOSN_NPU_PROT_DATA_RW_NSAID** +- **ETHOSN_NPU_PROT_DATA_RW_NSAID** Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for read/write access to the protected memory that contains inference data. -- **ARM_ETHOSN_NPU_PROT_DATA_RO_NSAID** +- **ETHOSN_NPU_PROT_DATA_RO_NSAID** Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for read-only access to the protected memory that contains inference data. -- **ARM_ETHOSN_NPU_NS_RW_DATA_NSAID** +- **ETHOSN_NPU_NS_RW_DATA_NSAID** Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for read/write access to the non-protected memory. -- **ARM_ETHOSN_NPU_NS_RO_DATA_NSAID** +- **ETHOSN_NPU_NS_RO_DATA_NSAID** Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for read-only access to the non-protected memory. -- **ARM_ETHOSN_NPU_FW_IMAGE_BASE** and **ARM_ETHOSN_NPU_FW_IMAGE_LIMIT** +- **ETHOSN_NPU_FW_IMAGE_BASE** and **ETHOSN_NPU_FW_IMAGE_LIMIT** Defines the physical address range that the NPU's firmware will be loaded into and executed from. @@ -634,10 +634,10 @@ enabled, the following constants and configuration must also be defined: - Add MMU mappings such that: - BL2 can write the NPU firmware into the region defined by - ``ARM_ETHOSN_NPU_FW_IMAGE_BASE`` and ``ARM_ETHOSN_NPU_FW_IMAGE_LIMIT`` + ``ETHOSN_NPU_FW_IMAGE_BASE`` and ``ETHOSN_NPU_FW_IMAGE_LIMIT`` - BL31 (SiP service) can read the NPU firmware from the same region -- Add the firmware image ID ``ARM_ETHOSN_NPU_FW_IMAGE_ID`` to the list of images +- Add the firmware image ID ``ETHOSN_NPU_FW_IMAGE_ID`` to the list of images loaded by BL2. Please see the reference implementation code for the Juno platform as an example.