fix(cpus): workaround for Neoverse V2 erratum 2779510

Neoverse V2 erratum 2779510 is a Cat B erratum that applies to
all revisions <= r0p1 and is fixed in r0p2. The workaround is to
set bit[47] of CPUACTLR3_EL1 which might have a small impact on
power and negligible impact on performance.

SDEN documentation:
https://developer.arm.com/documentation/SDEN2332927/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I6d937747bdcbf2913a64c4037f99918cbc466e80
This commit is contained in:
Bipin Ravi 2023-09-18 19:28:32 -05:00
parent b01140256b
commit ff342643bc
5 changed files with 23 additions and 2 deletions

View file

@ -536,6 +536,10 @@ For Neoverse V2, the following errata build flags are defined :
CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in
r0p2. r0p2.
- ``ERRATA_V2_2779510``: This applies errata 2779510 workaround to Neoverse-V2
CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in
r0p2.
- ``ERRATA_V2_2801372``: This applies errata 2801372 workaround to Neoverse-V2 - ``ERRATA_V2_2801372``: This applies errata 2801372 workaround to Neoverse-V2
CPU, this affects all configurations. This needs to be enabled for revisions CPU, this affects all configurations. This needs to be enabled for revisions
r0p0 and r0p1. It has been fixed in r0p2. r0p0 and r0p1. It has been fixed in r0p2.

View file

@ -37,4 +37,10 @@
#define NEOVERSE_V2_CPUACTLR2_EL1 S3_0_C15_C1_1 #define NEOVERSE_V2_CPUACTLR2_EL1 S3_0_C15_C1_1
#define NEOVERSE_V2_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0) #define NEOVERSE_V2_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0)
/*******************************************************************************
* CPU Auxiliary Control register 3 specific definitions.
******************************************************************************/
#define NEOVERSE_V2_CPUACTLR3_EL1 S3_0_C15_C1_2
#define NEOVERSE_V2_CPUACTLR3_EL1_BIT_47 (ULL(1) << 47)
#endif /* NEOVERSE_V2_H */ #endif /* NEOVERSE_V2_H */

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@ -35,6 +35,12 @@ workaround_reset_end neoverse_v2, ERRATUM(2719105)
check_erratum_ls neoverse_v2, ERRATUM(2719105), CPU_REV(0, 1) check_erratum_ls neoverse_v2, ERRATUM(2719105), CPU_REV(0, 1)
workaround_reset_start neoverse_v2, ERRATUM(2779510), ERRATA_V2_2779510
sysreg_bit_set NEOVERSE_V2_CPUACTLR3_EL1, NEOVERSE_V2_CPUACTLR3_EL1_BIT_47
workaround_reset_end neoverse_v2, ERRATUM(2779510)
check_erratum_ls neoverse_v2, ERRATUM(2779510), CPU_REV(0, 1)
workaround_runtime_start neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372 workaround_runtime_start neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372
/* dsb before isb of power down sequence */ /* dsb before isb of power down sequence */
dsb sy dsb sy

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@ -798,6 +798,10 @@ CPU_FLAG_LIST += ERRATA_V2_2719103
# to revisions r0p0 and r0p1. It is fixed in r0p2. # to revisions r0p0 and r0p1. It is fixed in r0p2.
CPU_FLAG_LIST += ERRATA_V2_2719105 CPU_FLAG_LIST += ERRATA_V2_2719105
# Flag to apply erratum 2779510 workaround during reset. This erratum applies
# to revisions r0p0 and r0p1. It is fixed in r0p2.
CPU_FLAG_LIST += ERRATA_V2_2779510
# Flag to apply erratum 2801372 workaround for all configurations. # Flag to apply erratum 2801372 workaround for all configurations.
# This erratum applies to revisions r0p0, r0p1. Fixed in r0p2. # This erratum applies to revisions r0p0, r0p1. Fixed in r0p2.
CPU_FLAG_LIST += ERRATA_V2_2801372 CPU_FLAG_LIST += ERRATA_V2_2801372

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@ -403,8 +403,9 @@ struct em_cpu_list cpu_list[] = {
[1] = {2719103, 0x00, 0x01, ERRATA_V2_2719103, \ [1] = {2719103, 0x00, 0x01, ERRATA_V2_2719103, \
ERRATA_NON_ARM_INTERCONNECT}, ERRATA_NON_ARM_INTERCONNECT},
[2] = {2719105, 0x00, 0x01, ERRATA_V2_2719105}, [2] = {2719105, 0x00, 0x01, ERRATA_V2_2719105},
[3] = {2801372, 0x00, 0x01, ERRATA_V2_2801372}, [3] = {2779510, 0x00, 0x01, ERRATA_V2_2779510},
[4 ... ERRATA_LIST_END] = UNDEF_ERRATA, [4] = {2801372, 0x00, 0x01, ERRATA_V2_2801372},
[5 ... ERRATA_LIST_END] = UNDEF_ERRATA,
} }
}, },
#endif /* NEOVERSE_V2_H_INC */ #endif /* NEOVERSE_V2_H_INC */