mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-22 20:38:03 +00:00
feat(n1sdp): enable trusted board boot on n1sdp
Move from RESET_TO_BL31 boot to a TBBR style boot on N1sdp. Signed-off-by: sahil <sahil@arm.com> Change-Id: I153ccb43a4a013830973c7a183825d62b372c65e
This commit is contained in:
sah01
sahil
parent
1d41fffff7
commit
fe2b37f685
11 changed files with 410 additions and 111 deletions
19
plat/arm/board/n1sdp/fdts/n1sdp_fw_config.dts
Normal file
19
plat/arm/board/n1sdp/fdts/n1sdp_fw_config.dts
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@ -0,0 +1,19 @@
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/*
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* Copyright (c) 2022, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/tbbr/tbbr_img_def.h>
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/dts-v1/;
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/ {
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dtb-registry {
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compatible = "fconf,dyn_cfg-dtb_registry";
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tb_fw-config {
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load-address = <0x0 0x4001300>;
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max-size = <0x200>;
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id = <TB_FW_CONFIG_ID>;
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};
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};
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};
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27
plat/arm/board/n1sdp/fdts/n1sdp_tb_fw_config.dts
Normal file
27
plat/arm/board/n1sdp/fdts/n1sdp_tb_fw_config.dts
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@ -0,0 +1,27 @@
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/*
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* Copyright (c) 2022, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/dts-v1/;
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/ {
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tb_fw-config {
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compatible = "arm,tb_fw";
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/* Disable authentication for development */
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disable_auth = <0x0>;
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/*
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* The following two entries are placeholders for Mbed TLS
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* heap information. The default values don't matter since
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* they will be overwritten by BL1.
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* In case of having shared Mbed TLS heap between BL1 and BL2,
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* BL1 will populate these two properties with the respective
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* info about the shared heap. This info will be available for
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* BL2 in order to locate and re-use the heap.
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*/
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mbedtls_heap_addr = <0x0 0x0>;
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mbedtls_heap_size = <0x0>;
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};
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};
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2018-2022, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -27,6 +27,27 @@
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#define PLAT_ARM_DRAM2_BASE ULL(0x8080000000)
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#define PLAT_ARM_DRAM2_SIZE ULL(0xF80000000)
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#define MAX_IO_DEVICES U(3)
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#define MAX_IO_HANDLES U(4)
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#define PLAT_ARM_FLASH_IMAGE_BASE 0x18200000
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#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE 0x00800000
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#define PLAT_ARM_NVM_BASE 0x18200000
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#define PLAT_ARM_NVM_SIZE 0x00800000
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#if defined NS_BL1U_BASE
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# undef NS_BL1U_BASE
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# define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + UL(0x00800000))
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#endif
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/* Non-volatile counters */
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#define SOC_TRUSTED_NVCTR_BASE 0x7fe70000
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#define TFW_NVCTR_BASE (SOC_TRUSTED_NVCTR_BASE)
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#define TFW_NVCTR_SIZE U(4)
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#define NTFW_CTR_BASE (SOC_TRUSTED_NVCTR_BASE + 0x0004)
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#define NTFW_CTR_SIZE U(4)
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/* N1SDP remote chip at 4 TB offset */
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#define PLAT_ARM_REMOTE_CHIP_OFFSET (ULL(1) << 42)
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@ -59,8 +80,42 @@
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#define PLAT_CSS_SCP_COM_SHARED_MEM_BASE 0x45400000
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#endif
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#define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00080000 /* 512 KB */
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#define PLAT_ARM_MAX_BL31_SIZE 0X20000
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/*
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* Trusted SRAM in N1SDP is 512 KB but only the bottom 384 KB
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* is used for trusted board boot flow. The top 128 KB is used
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* to load AP-BL1 image.
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*/
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#define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00060000 /* 384 KB */
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/*
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* PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
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* plus a little space for growth.
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*/
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#define PLAT_ARM_MAX_BL1_RW_SIZE 0xE000
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/*
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* PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page
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*/
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#if USE_ROMLIB
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# define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0x1000
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# define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0xe000
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#else
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# define PLAT_ARM_MAX_ROMLIB_RW_SIZE U(0)
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# define PLAT_ARM_MAX_ROMLIB_RO_SIZE U(0)
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#endif
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/*
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* PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
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* little space for growth.
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*/
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#if TRUSTED_BOARD_BOOT
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# define PLAT_ARM_MAX_BL2_SIZE 0x20000
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#else
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# define PLAT_ARM_MAX_BL2_SIZE 0x14000
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#endif
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#define PLAT_ARM_MAX_BL31_SIZE UL(0x3B000)
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/*******************************************************************************
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* N1SDP topology related constants
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@ -83,10 +138,48 @@
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* PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
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* plat_arm_mmap array defined for each BL stage.
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*/
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#define PLAT_ARM_MMAP_ENTRIES 9
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#define MAX_XLAT_TABLES 10
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#ifdef IMAGE_BL1
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# define PLAT_ARM_MMAP_ENTRIES U(6)
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# define MAX_XLAT_TABLES U(5)
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#endif
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#ifdef IMAGE_BL2
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# define PLAT_ARM_MMAP_ENTRIES U(11)
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# define MAX_XLAT_TABLES U(10)
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#endif
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#ifdef IMAGE_BL31
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# define PLAT_ARM_MMAP_ENTRIES U(12)
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# define MAX_XLAT_TABLES U(12)
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#endif
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/*
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* Size of cacheable stacks
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*/
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#if defined(IMAGE_BL1)
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# if TRUSTED_BOARD_BOOT
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# define PLATFORM_STACK_SIZE 0x1000
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# else
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# define PLATFORM_STACK_SIZE 0x440
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# endif
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#elif defined(IMAGE_BL2)
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# if TRUSTED_BOARD_BOOT
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# define PLATFORM_STACK_SIZE 0x1000
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# else
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# define PLATFORM_STACK_SIZE 0x400
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# endif
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#elif defined(IMAGE_BL2U)
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# define PLATFORM_STACK_SIZE 0x400
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#elif defined(IMAGE_BL31)
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# if SPM_MM
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# define PLATFORM_STACK_SIZE 0x500
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# else
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# define PLATFORM_STACK_SIZE 0x400
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# endif
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#elif defined(IMAGE_BL32)
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# define PLATFORM_STACK_SIZE 0x440
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#endif
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#define PLAT_ARM_NSTIMER_FRAME_ID 0
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#define PLAT_CSS_MHU_BASE 0x45000000
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@ -106,6 +199,10 @@
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PLAT_ARM_REMOTE_CHIP_OFFSET
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#define N1SDP_REMOTE_DEVICE_SIZE N1SDP_DEVICE_SIZE
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/* Real base is 0x0. Changed to load BL1 at this address */
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# define PLAT_ARM_TRUSTED_ROM_BASE 0x04060000
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# define PLAT_ARM_TRUSTED_ROM_SIZE 0x00020000 /* 128KB */
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#define N1SDP_MAP_DEVICE MAP_REGION_FLAT( \
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N1SDP_DEVICE_BASE, \
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N1SDP_DEVICE_SIZE, \
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19
plat/arm/board/n1sdp/n1sdp_bl1_setup.c
Normal file
19
plat/arm/board/n1sdp/n1sdp_bl1_setup.c
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@ -0,0 +1,19 @@
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/*
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* Copyright (c) 2022, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <plat/arm/common/plat_arm.h>
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/*******************************************************************************
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* Perform any BL1 specific platform actions.
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******************************************************************************/
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void soc_css_init_nic400(void)
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{
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}
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void soc_css_init_pcie(void)
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{
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}
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89
plat/arm/board/n1sdp/n1sdp_bl2_setup.c
Normal file
89
plat/arm/board/n1sdp/n1sdp_bl2_setup.c
Normal file
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@ -0,0 +1,89 @@
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/*
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* Copyright (c) 2022, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/debug.h>
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#include <drivers/arm/css/sds.h>
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#include <lib/mmio.h>
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#include <lib/utils.h>
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#include "n1sdp_def.h"
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#include <plat/arm/common/plat_arm.h>
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struct n1sdp_plat_info {
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bool multichip_mode;
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uint8_t secondary_count;
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uint8_t local_ddr_size;
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uint8_t remote_ddr_size;
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} __packed;
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/*
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* N1SDP platform supports RDIMMs with ECC capability. To use the ECC
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* capability, the entire DDR memory space has to be zeroed out before
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* enabling the ECC bits in DMC620. Zeroing out several gigabytes of
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* memory from SCP is quite time consuming so the following function
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* is added to zero out the DDR memory from application processor which is
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* much faster compared to SCP.
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*/
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void dmc_ecc_setup(uint8_t ddr_size_gb)
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{
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uint64_t dram2_size;
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dram2_size = (ddr_size_gb * 1024UL * 1024UL * 1024UL) -
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ARM_DRAM1_SIZE;
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INFO("Zeroing DDR memories\n");
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zero_normalmem((void *)ARM_DRAM1_BASE, ARM_DRAM1_SIZE);
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flush_dcache_range(ARM_DRAM1_BASE, ARM_DRAM1_SIZE);
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zero_normalmem((void *)ARM_DRAM2_BASE, dram2_size);
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flush_dcache_range(ARM_DRAM2_BASE, dram2_size);
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INFO("Enabling ECC on DMCs\n");
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/* Set DMCs to CONFIG state before writing ERR0CTLR0 register */
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mmio_write_32(N1SDP_DMC0_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_CONFIG);
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mmio_write_32(N1SDP_DMC1_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_CONFIG);
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/* Enable ECC in DMCs */
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mmio_setbits_32(N1SDP_DMC0_ERR0CTLR0_REG, N1SDP_DMC_ERR0CTLR0_ECC_EN);
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mmio_setbits_32(N1SDP_DMC1_ERR0CTLR0_REG, N1SDP_DMC_ERR0CTLR0_ECC_EN);
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/* Set DMCs to READY state */
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mmio_write_32(N1SDP_DMC0_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_READY);
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mmio_write_32(N1SDP_DMC1_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_READY);
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}
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void bl2_platform_setup(void)
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{
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int ret;
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struct n1sdp_plat_info plat_info;
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ret = sds_init();
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if (ret != SDS_OK) {
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ERROR("SDS initialization failed\n");
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panic();
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}
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ret = sds_struct_read(N1SDP_SDS_PLATFORM_INFO_STRUCT_ID,
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N1SDP_SDS_PLATFORM_INFO_OFFSET,
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&plat_info,
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N1SDP_SDS_PLATFORM_INFO_SIZE,
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SDS_ACCESS_MODE_NON_CACHED);
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if (ret != SDS_OK) {
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ERROR("Error getting platform info from SDS\n");
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panic();
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}
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/* Validate plat_info SDS */
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if ((plat_info.local_ddr_size == 0)
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|| (plat_info.local_ddr_size > N1SDP_MAX_DDR_CAPACITY_GB)
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|| (plat_info.remote_ddr_size > N1SDP_MAX_DDR_CAPACITY_GB)
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|| (plat_info.secondary_count > N1SDP_MAX_SECONDARY_COUNT)) {
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ERROR("platform info SDS is corrupted\n");
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panic();
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}
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dmc_ecc_setup(plat_info.local_ddr_size);
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arm_bl2_platform_setup();
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}
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@ -1,11 +1,9 @@
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/*
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* Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2018-2022, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <platform_def.h>
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#include <common/debug.h>
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#include <drivers/arm/css/css_mhu_doorbell.h>
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#include <drivers/arm/css/scmi.h>
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@ -16,6 +14,7 @@
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#include <plat/arm/common/plat_arm.h>
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#include "n1sdp_def.h"
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#include <platform_def.h>
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/*
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* Platform information structure stored in SDS.
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@ -24,28 +23,17 @@
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* enabling the ECC capability as well as information
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* about multichip setup
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* - multichip mode
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* - slave_count
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* - secondary_count
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* - Local DDR size in GB, DDR memory in master board
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* - Remote DDR size in GB, DDR memory in slave board
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* - Remote DDR size in GB, DDR memory in secondary board
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*/
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struct n1sdp_plat_info {
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bool multichip_mode;
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uint8_t slave_count;
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uint8_t secondary_count;
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uint8_t local_ddr_size;
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uint8_t remote_ddr_size;
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} __packed;
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/*
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* BL33 image information structure stored in SDS.
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* This structure holds the source & destination addresses and
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* the size of the BL33 image which will be loaded by BL31.
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*/
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struct n1sdp_bl33_info {
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uint32_t bl33_src_addr;
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uint32_t bl33_dst_addr;
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uint32_t bl33_size;
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};
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static scmi_channel_plat_info_t n1sdp_scmi_plat_info = {
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.scmi_mbx_mem = N1SDP_SCMI_PAYLOAD_BASE,
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.db_reg_addr = PLAT_CSS_MHU_BASE + CSS_SCMI_MHU_DB_REG_OFF,
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@ -90,38 +78,10 @@ const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
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* enabling the ECC bits in DMC620. Zeroing out several gigabytes of
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* memory from SCP is quite time consuming so the following function
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* is added to zero out the DDR memory from application processor which is
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* much faster compared to SCP. BL33 binary cannot be copied to DDR memory
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* before enabling ECC so copy_bl33 function is added to copy BL33 binary
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* from IOFPGA-DDR3 memory to main DDR4 memory.
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* much faster compared to SCP. Local DDR memory is zeroed out during BL2
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* stage. If remote chip is connected, it's DDR memory is zeroed out here.
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*/
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void dmc_ecc_setup(uint8_t ddr_size_gb)
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{
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uint64_t dram2_size;
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dram2_size = (ddr_size_gb * 1024UL * 1024UL * 1024UL) -
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ARM_DRAM1_SIZE;
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INFO("Zeroing DDR memories\n");
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zero_normalmem((void *)ARM_DRAM1_BASE, ARM_DRAM1_SIZE);
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flush_dcache_range(ARM_DRAM1_BASE, ARM_DRAM1_SIZE);
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zero_normalmem((void *)ARM_DRAM2_BASE, dram2_size);
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flush_dcache_range(ARM_DRAM2_BASE, dram2_size);
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INFO("Enabling ECC on DMCs\n");
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/* Set DMCs to CONFIG state before writing ERR0CTLR0 register */
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mmio_write_32(N1SDP_DMC0_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_CONFIG);
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mmio_write_32(N1SDP_DMC1_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_CONFIG);
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/* Enable ECC in DMCs */
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mmio_setbits_32(N1SDP_DMC0_ERR0CTLR0_REG, N1SDP_DMC_ERR0CTLR0_ECC_EN);
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mmio_setbits_32(N1SDP_DMC1_ERR0CTLR0_REG, N1SDP_DMC_ERR0CTLR0_ECC_EN);
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/* Set DMCs to READY state */
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mmio_write_32(N1SDP_DMC0_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_READY);
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mmio_write_32(N1SDP_DMC1_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_READY);
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}
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void remote_dmc_ecc_setup(uint8_t remote_ddr_size)
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{
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uint64_t remote_dram2_size;
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@ -154,22 +114,6 @@ void remote_dmc_ecc_setup(uint8_t remote_ddr_size)
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mmio_write_32(N1SDP_REMOTE_DMC1_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_READY);
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}
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void copy_bl33(uint32_t src, uint32_t dst, uint32_t size)
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{
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uint32_t i;
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INFO("Copying BL33 to DDR memory\n");
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for (i = 0; i < size; i = i + 8)
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mmio_write_64((dst + i), mmio_read_64(src + i));
|
||||
|
||||
for (i = 0; i < size; i = i + 8) {
|
||||
if (mmio_read_64(src + i) != mmio_read_64(dst + i)) {
|
||||
ERROR("Copy failed!\n");
|
||||
panic();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void n1sdp_bl31_multichip_setup(void)
|
||||
{
|
||||
plat_arm_override_gicr_frames(n1sdp_multichip_gicr_frames);
|
||||
|
|
@ -180,7 +124,6 @@ void bl31_platform_setup(void)
|
|||
{
|
||||
int ret;
|
||||
struct n1sdp_plat_info plat_info;
|
||||
struct n1sdp_bl33_info bl33_info;
|
||||
|
||||
ret = sds_init();
|
||||
if (ret != SDS_OK) {
|
||||
|
|
@ -201,35 +144,20 @@ void bl31_platform_setup(void)
|
|||
if ((plat_info.local_ddr_size == 0)
|
||||
|| (plat_info.local_ddr_size > N1SDP_MAX_DDR_CAPACITY_GB)
|
||||
|| (plat_info.remote_ddr_size > N1SDP_MAX_DDR_CAPACITY_GB)
|
||||
|| (plat_info.slave_count > N1SDP_MAX_SLAVE_COUNT)) {
|
||||
|| (plat_info.secondary_count > N1SDP_MAX_SECONDARY_COUNT)) {
|
||||
ERROR("platform info SDS is corrupted\n");
|
||||
panic();
|
||||
}
|
||||
|
||||
if (plat_info.multichip_mode) {
|
||||
n1sdp_multichip_data.chip_count = plat_info.slave_count + 1;
|
||||
n1sdp_multichip_data.chip_count = plat_info.secondary_count + 1;
|
||||
n1sdp_bl31_multichip_setup();
|
||||
}
|
||||
arm_bl31_platform_setup();
|
||||
|
||||
dmc_ecc_setup(plat_info.local_ddr_size);
|
||||
|
||||
/* Check if remote memory is present */
|
||||
if ((plat_info.multichip_mode) && (plat_info.remote_ddr_size != 0))
|
||||
remote_dmc_ecc_setup(plat_info.remote_ddr_size);
|
||||
|
||||
ret = sds_struct_read(N1SDP_SDS_BL33_INFO_STRUCT_ID,
|
||||
N1SDP_SDS_BL33_INFO_OFFSET,
|
||||
&bl33_info,
|
||||
N1SDP_SDS_BL33_INFO_SIZE,
|
||||
SDS_ACCESS_MODE_NON_CACHED);
|
||||
if (ret != SDS_OK) {
|
||||
ERROR("Error getting BL33 info from SDS\n");
|
||||
panic();
|
||||
}
|
||||
copy_bl33(bl33_info.bl33_src_addr,
|
||||
bl33_info.bl33_dst_addr,
|
||||
bl33_info.bl33_size);
|
||||
/*
|
||||
* Pass platform information to BL33. This method is followed as
|
||||
* currently there is no BL1/BL2 involved in boot flow of N1SDP.
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2018-2022, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -20,12 +20,7 @@
|
|||
#define N1SDP_SDS_PLATFORM_INFO_OFFSET 0
|
||||
#define N1SDP_SDS_PLATFORM_INFO_SIZE 4
|
||||
#define N1SDP_MAX_DDR_CAPACITY_GB 64
|
||||
#define N1SDP_MAX_SLAVE_COUNT 16
|
||||
|
||||
/* SDS BL33 image information defines */
|
||||
#define N1SDP_SDS_BL33_INFO_STRUCT_ID 9
|
||||
#define N1SDP_SDS_BL33_INFO_OFFSET 0
|
||||
#define N1SDP_SDS_BL33_INFO_SIZE 12
|
||||
#define N1SDP_MAX_SECONDARY_COUNT 16
|
||||
|
||||
/* DMC memory command registers */
|
||||
#define N1SDP_DMC0_MEMC_CMD_REG 0x4E000008
|
||||
|
|
|
|||
17
plat/arm/board/n1sdp/n1sdp_err.c
Normal file
17
plat/arm/board/n1sdp/n1sdp_err.c
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
/*
|
||||
* Copyright (c) 2022, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <plat/arm/common/plat_arm.h>
|
||||
|
||||
/*
|
||||
* n1sdp error handler
|
||||
*/
|
||||
void __dead2 plat_arm_error_handler(int err)
|
||||
{
|
||||
while (true) {
|
||||
wfi();
|
||||
}
|
||||
}
|
||||
|
|
@ -1,16 +1,13 @@
|
|||
/*
|
||||
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2018-2022, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <platform_def.h>
|
||||
#include <assert.h>
|
||||
|
||||
#include <common/bl_common.h>
|
||||
#include <common/debug.h>
|
||||
#include <plat/arm/common/plat_arm.h>
|
||||
#include <plat/common/platform.h>
|
||||
#include <drivers/arm/sbsa.h>
|
||||
#include <plat/arm/common/plat_arm.h>
|
||||
|
||||
#include "n1sdp_def.h"
|
||||
|
||||
|
|
@ -19,17 +16,51 @@
|
|||
* Replace or extend the below regions as required
|
||||
*/
|
||||
|
||||
#if IMAGE_BL1
|
||||
const mmap_region_t plat_arm_mmap[] = {
|
||||
ARM_MAP_SHARED_RAM,
|
||||
N1SDP_MAP_DEVICE,
|
||||
N1SDP_MAP_NS_SRAM,
|
||||
ARM_MAP_DRAM1,
|
||||
{0}
|
||||
};
|
||||
#endif
|
||||
|
||||
#if IMAGE_BL2
|
||||
const mmap_region_t plat_arm_mmap[] = {
|
||||
ARM_MAP_SHARED_RAM,
|
||||
N1SDP_MAP_DEVICE,
|
||||
N1SDP_MAP_NS_SRAM,
|
||||
ARM_MAP_DRAM1,
|
||||
ARM_MAP_DRAM2,
|
||||
#if TRUSTED_BOARD_BOOT && !BL2_AT_EL3
|
||||
ARM_MAP_BL1_RW,
|
||||
#endif
|
||||
{0}
|
||||
};
|
||||
#endif
|
||||
|
||||
#if IMAGE_BL31
|
||||
const mmap_region_t plat_arm_mmap[] = {
|
||||
ARM_MAP_SHARED_RAM,
|
||||
N1SDP_MAP_DEVICE,
|
||||
N1SDP_MAP_NS_SRAM,
|
||||
N1SDP_MAP_REMOTE_DEVICE,
|
||||
N1SDP_MAP_REMOTE_DRAM1,
|
||||
N1SDP_MAP_REMOTE_DRAM2,
|
||||
{0}
|
||||
};
|
||||
#endif
|
||||
|
||||
#if TRUSTED_BOARD_BOOT
|
||||
int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
|
||||
{
|
||||
assert(heap_addr != NULL);
|
||||
assert(heap_size != NULL);
|
||||
|
||||
return arm_get_mbedtls_heap(heap_addr, heap_size);
|
||||
}
|
||||
#endif
|
||||
|
||||
void plat_arm_secure_wdt_start(void)
|
||||
{
|
||||
|
|
|
|||
54
plat/arm/board/n1sdp/n1sdp_trusted_boot.c
Normal file
54
plat/arm/board/n1sdp/n1sdp_trusted_boot.c
Normal file
|
|
@ -0,0 +1,54 @@
|
|||
/*
|
||||
* Copyright (c) 2022, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <plat/arm/common/plat_arm.h>
|
||||
|
||||
/*
|
||||
* Return the non-volatile counter value stored in the platform. The cookie
|
||||
* will contain the OID of the counter in the certificate.
|
||||
*
|
||||
* Return: 0 = success, Otherwise = error
|
||||
*/
|
||||
int plat_get_nv_ctr(void *cookie, unsigned int *nv_ctr)
|
||||
{
|
||||
*nv_ctr = N1SDP_FW_NVCTR_VAL;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Store a new non-volatile counter value. By default on ARM development
|
||||
* platforms, the non-volatile counters are RO and cannot be modified. We expect
|
||||
* the values in the certificates to always match the RO values so that this
|
||||
* function is never called.
|
||||
*
|
||||
* Return: 0 = success, Otherwise = error
|
||||
*/
|
||||
int plat_set_nv_ctr(void *cookie, unsigned int nv_ctr)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* Return the ROTPK hash in the following ASN.1 structure in DER format:
|
||||
*
|
||||
* AlgorithmIdentifier ::= SEQUENCE {
|
||||
* algorithm OBJECT IDENTIFIER,
|
||||
* parameters ANY DEFINED BY algorithm OPTIONAL
|
||||
* }
|
||||
*
|
||||
* DigestInfo ::= SEQUENCE {
|
||||
* digestAlgorithm AlgorithmIdentifier,
|
||||
* digest OCTET STRING
|
||||
* }
|
||||
*/
|
||||
int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len,
|
||||
unsigned int *flags)
|
||||
{
|
||||
return arm_get_rotpk_info(cookie, key_ptr, key_len, flags);
|
||||
}
|
||||
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
#
|
||||
# Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
|
||||
# Copyright (c) 2018-2022, Arm Limited. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
|
@ -28,7 +28,19 @@ N1SDP_GIC_SOURCES := ${GICV3_SOURCES} \
|
|||
PLAT_BL_COMMON_SOURCES := ${N1SDP_BASE}/n1sdp_plat.c \
|
||||
${N1SDP_BASE}/aarch64/n1sdp_helper.S
|
||||
|
||||
BL1_SOURCES += drivers/arm/sbsa/sbsa.c
|
||||
BL1_SOURCES := ${N1SDP_CPU_SOURCES} \
|
||||
${INTERCONNECT_SOURCES} \
|
||||
${N1SDP_BASE}/n1sdp_err.c \
|
||||
${N1SDP_BASE}/n1sdp_trusted_boot.c \
|
||||
${N1SDP_BASE}/n1sdp_bl1_setup.c \
|
||||
drivers/arm/sbsa/sbsa.c
|
||||
|
||||
BL2_SOURCES := ${N1SDP_BASE}/n1sdp_security.c \
|
||||
${N1SDP_BASE}/n1sdp_err.c \
|
||||
${N1SDP_BASE}/n1sdp_trusted_boot.c \
|
||||
lib/utils/mem_region.c \
|
||||
${N1SDP_BASE}/n1sdp_bl2_setup.c \
|
||||
drivers/arm/css/sds/sds.c
|
||||
|
||||
BL31_SOURCES := ${N1SDP_CPU_SOURCES} \
|
||||
${INTERCONNECT_SOURCES} \
|
||||
|
|
@ -39,19 +51,31 @@ BL31_SOURCES := ${N1SDP_CPU_SOURCES} \
|
|||
drivers/arm/css/sds/sds.c
|
||||
|
||||
FDT_SOURCES += fdts/${PLAT}-single-chip.dts \
|
||||
fdts/${PLAT}-multi-chip.dts
|
||||
fdts/${PLAT}-multi-chip.dts \
|
||||
${N1SDP_BASE}/fdts/n1sdp_fw_config.dts \
|
||||
${N1SDP_BASE}/fdts/n1sdp_tb_fw_config.dts
|
||||
|
||||
FW_CONFIG := ${BUILD_PLAT}/fdts/n1sdp_fw_config.dtb
|
||||
TB_FW_CONFIG := ${BUILD_PLAT}/fdts/n1sdp_tb_fw_config.dtb
|
||||
|
||||
# Add the FW_CONFIG to FIP and specify the same to certtool
|
||||
$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG}))
|
||||
# Add the TB_FW_CONFIG to FIP and specify the same to certtool
|
||||
$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG}))
|
||||
|
||||
# Setting to 0 as no NVCTR in N1SDP
|
||||
N1SDP_FW_NVCTR_VAL := 0
|
||||
TFW_NVCTR_VAL := ${N1SDP_FW_NVCTR_VAL}
|
||||
NTFW_NVCTR_VAL := ${N1SDP_FW_NVCTR_VAL}
|
||||
|
||||
# Add N1SDP_FW_NVCTR_VAL
|
||||
$(eval $(call add_define,N1SDP_FW_NVCTR_VAL))
|
||||
|
||||
# TF-A not required to load the SCP Images
|
||||
override CSS_LOAD_SCP_IMAGES := 0
|
||||
|
||||
# BL1/BL2 Image not a part of the capsule Image for n1sdp
|
||||
override NEED_BL1 := no
|
||||
override NEED_BL2 := no
|
||||
override NEED_BL2U := no
|
||||
|
||||
#TFA for n1sdp starts from BL31
|
||||
override RESET_TO_BL31 := 1
|
||||
|
||||
# 32 bit mode not supported
|
||||
override CTX_INCLUDE_AARCH32_REGS := 0
|
||||
|
||||
|
|
@ -73,4 +97,3 @@ NEOVERSE_Nx_EXTERNAL_LLC := 1
|
|||
include plat/arm/common/arm_common.mk
|
||||
include plat/arm/css/common/css_common.mk
|
||||
include plat/arm/board/common/board_common.mk
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue