mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-16 09:34:18 +00:00
Remove all other deprecated interfaces and files
Change-Id: Icd1cdd42afdc78895a9be6c46b414b0a155cfa63 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
This commit is contained in:
Antonio Nino Diaz
parent
61d2b40d28
commit
fe199e3bac
27 changed files with 0 additions and 348 deletions
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@ -60,16 +60,6 @@ ifeq (${TF_MBEDTLS_KEY_ALG},)
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endif
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endif
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# If MBEDTLS_KEY_ALG build flag is defined use it to set TF_MBEDTLS_KEY_ALG for
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# backward compatibility
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ifdef MBEDTLS_KEY_ALG
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ifeq (${ERROR_DEPRECATED},1)
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$(error "MBEDTLS_KEY_ALG is deprecated. Please use the new build flag TF_MBEDTLS_KEY_ALG")
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endif
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$(warning "MBEDTLS_KEY_ALG is deprecated. Please use the new build flag TF_MBEDTLS_KEY_ALG")
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TF_MBEDTLS_KEY_ALG := ${MBEDTLS_KEY_ALG}
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endif
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ifeq (${HASH_ALG}, sha384)
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TF_MBEDTLS_HASH_ALG_ID := TF_MBEDTLS_SHA384
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else ifeq (${HASH_ALG}, sha512)
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@ -97,19 +97,6 @@
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.fill \label + (32 * 4) - .
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.endm
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/*
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* This macro verifies that the given vector doesn't exceed the
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* architectural limit of 32 instructions. This is meant to be placed
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* immediately after the last instruction in the vector. It takes the
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* vector entry as the parameter
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*/
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.macro check_vector_size since
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#if ERROR_DEPRECATED
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.error "check_vector_size must not be used. Use end_vector_entry instead"
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#endif
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end_vector_entry \since
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.endm
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/*
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* This macro calculates the base address of the current CPU's MP stack
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* using the plat_my_core_pos() index, the name of the stack storage
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@ -30,9 +30,6 @@
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/* Prevent mbed TLS from using snprintf so that it can use tf_snprintf. */
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#define MBEDTLS_PLATFORM_SNPRINTF_ALT
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#if !ERROR_DEPRECATED
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#define MBEDTLS_PKCS1_V15
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#endif
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#define MBEDTLS_PKCS1_V21
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#define MBEDTLS_X509_ALLOW_UNSUPPORTED_CRITICAL_EXTENSION
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@ -126,10 +126,6 @@
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#define SDCR_SPD_ENABLE U(0x3)
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#define SDCR_RESET_VAL U(0x0)
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#if !ERROR_DEPRECATED
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#define SDCR_DEF_VAL SDCR_SPD(SDCR_SPD_DISABLE)
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#endif
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/* HSCTLR definitions */
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#define HSCTLR_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
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(U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
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@ -220,10 +216,6 @@
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#define NSASEDIS_BIT (U(1) << 15)
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#define NSTRCDIS_BIT (U(1) << 20)
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/* NOTE: correct typo in the definitions */
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#if !ERROR_DEPRECATED
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#define NASCR_CP11_BIT (U(1) << 11)
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#define NASCR_CP10_BIT (U(1) << 10)
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#endif
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#define NSACR_CP11_BIT (U(1) << 11)
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#define NSACR_CP10_BIT (U(1) << 10)
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#define NSACR_IMP_DEF_MASK (U(0x7) << 16)
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@ -1,14 +0,0 @@
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/*
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* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __SMCC_HELPERS_H__
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#define __SMCC_HELPERS_H__
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#if !ERROR_DEPRECATED
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#include <smccc_helpers.h>
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#endif
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#endif /* __SMCC_HELPERS_H__ */
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@ -1,15 +0,0 @@
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/*
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* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __SMCC_MACROS_S__
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#define __SMCC_MACROS_S__
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#if !ERROR_DEPRECATED
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#include <smccc_macros.S>
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#define smcc_save_gp_mode_regs smccc_save_gp_mode_regs
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#endif
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#endif /* __SMCC_MACROS_S__ */
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@ -245,10 +245,6 @@
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#define MDCR_TPM_BIT (U(1) << 6)
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#define MDCR_EL3_RESET_VAL U(0x0)
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#if !ERROR_DEPRECATED
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#define MDCR_DEF_VAL (MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE))
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#endif
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/* MDCR_EL2 definitions */
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#define MDCR_EL2_TPMS (U(1) << 14)
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#define MDCR_EL2_E2PB(x) ((x) << 12)
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@ -1,14 +0,0 @@
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/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __SMCC_HELPERS_H__
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#define __SMCC_HELPERS_H__
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#if !ERROR_DEPRECATED
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#include <smccc_helpers.h>
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#endif
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#endif /* __SMCC_HELPERS_H__ */
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@ -67,16 +67,4 @@
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******************************************************************************/
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#define CORTEX_A53_L2MERRSR p15, 3, c15
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#if !ERROR_DEPRECATED
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/*
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* These registers were previously wrongly named. Provide previous definitions so
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* as not to break platforms that continue using them.
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*/
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#define CORTEX_A53_ACTLR CORTEX_A53_CPUACTLR
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#define CORTEX_A53_ACTLR_ENDCCASCI_SHIFT CORTEX_A53_CPUACTLR_ENDCCASCI_SHIFT
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#define CORTEX_A53_ACTLR_ENDCCASCI CORTEX_A53_CPUACTLR_ENDCCASCI
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#define CORTEX_A53_ACTLR_DTAH CORTEX_A53_CPUACTLR_DTAH
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#endif /* !ERROR_DEPRECATED */
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#endif /* __CORTEX_A53_H__ */
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@ -79,22 +79,4 @@
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******************************************************************************/
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#define CORTEX_A57_L2MERRSR p15, 3, c15
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#if !ERROR_DEPRECATED
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/*
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* These registers were previously wrongly named. Provide previous definitions so
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* as not to break platforms that continue using them.
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*/
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#define CORTEX_A57_ACTLR CORTEX_A57_CPUACTLR
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#define CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_DMB
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#define CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE CORTEX_A57_CPUACTLR_GRE_NGRE_AS_NGNRE
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#define CORTEX_A57_ACTLR_DIS_OVERREAD CORTEX_A57_CPUACTLR_DIS_OVERREAD
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#define CORTEX_A57_ACTLR_NO_ALLOC_WBWA CORTEX_A57_CPUACTLR_NO_ALLOC_WBWA
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#define CORTEX_A57_ACTLR_DCC_AS_DCCI CORTEX_A57_CPUACTLR_DCC_AS_DCCI
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#define CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH CORTEX_A57_CPUACTLR_FORCE_FPSCR_FLUSH
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#define CORTEX_A57_ACTLR_DIS_STREAMING CORTEX_A57_CPUACTLR_DIS_STREAMING
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#define CORTEX_A57_ACTLR_DIS_L1_STREAMING CORTEX_A57_CPUACTLR_DIS_L1_STREAMING
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#define CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR CORTEX_A57_CPUACTLR_DIS_INDIRECT_PREDICTOR
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#endif /* !ERROR_DEPRECATED */
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#endif /* __CORTEX_A57_H__ */
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@ -54,16 +54,4 @@
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******************************************************************************/
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#define CORTEX_A72_L2MERRSR p15, 3, c15
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#if !ERROR_DEPRECATED
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/*
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* These registers were previously wrongly named. Provide previous definitions so
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* as not to break platforms that continue using them.
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*/
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#define CORTEX_A72_ACTLR CORTEX_A72_CPUACTLR
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#define CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH CORTEX_A72_CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH
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#define CORTEX_A72_ACTLR_NO_ALLOC_WBWA CORTEX_A72_CPUACTLR_NO_ALLOC_WBWA
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#define CORTEX_A72_ACTLR_DCC_AS_DCCI CORTEX_A72_CPUACTLR_DCC_AS_DCCI
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#endif /* !ERROR_DEPRECATED */
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#endif /* __CORTEX_A72_H__ */
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@ -71,21 +71,4 @@
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******************************************************************************/
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#define CORTEX_A53_L2MERRSR_EL1 S3_1_C15_C2_3
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#if !ERROR_DEPRECATED
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/*
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* These registers were previously wrongly named. Provide previous definitions
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* so as not to break platforms that continue using them.
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*/
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#define CORTEX_A53_ACTLR_EL1 CORTEX_A53_CPUACTLR_EL1
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#define CORTEX_A53_ACTLR_ENDCCASCI_SHIFT CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT
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#define CORTEX_A53_ACTLR_ENDCCASCI CORTEX_A53_CPUACTLR_EL1_ENDCCASCI
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#define CORTEX_A53_ACTLR_RADIS_SHIFT CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT
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#define CORTEX_A53_ACTLR_RADIS CORTEX_A53_CPUACTLR_EL1_RADIS
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#define CORTEX_A53_ACTLR_L1RADIS_SHIFT CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT
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#define CORTEX_A53_ACTLR_L1RADIS CORTEX_A53_CPUACTLR_EL1_L1RADIS
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#define CORTEX_A53_ACTLR_DTAH_SHIFT CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT
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#define CORTEX_A53_ACTLR_DTAH CORTEX_A53_CPUACTLR_EL1_DTAH
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#endif /* !ERROR_DEPRECATED */
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#endif /* __CORTEX_A53_H__ */
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@ -81,22 +81,4 @@
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******************************************************************************/
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#define CORTEX_A57_L2MERRSR_EL1 S3_1_C15_C2_3
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#if !ERROR_DEPRECATED
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/*
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* These registers were previously wrongly named. Provide previous definitions so
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* as not to break platforms that continue using them.
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*/
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#define CORTEX_A57_ACTLR_EL1 CORTEX_A57_CPUACTLR_EL1
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#define CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB
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#define CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE
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#define CORTEX_A57_ACTLR_DIS_OVERREAD CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD
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#define CORTEX_A57_ACTLR_NO_ALLOC_WBWA CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA
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#define CORTEX_A57_ACTLR_DCC_AS_DCCI CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI
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#define CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH
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#define CORTEX_A57_ACTLR_DIS_STREAMING CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING
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#define CORTEX_A57_ACTLR_DIS_L1_STREAMING CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING
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#define CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR
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#endif /* !ERROR_DEPRECATED */
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#endif /* __CORTEX_A57_H__ */
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@ -61,16 +61,4 @@
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******************************************************************************/
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#define CORTEX_A72_L2MERRSR_EL1 S3_1_C15_C2_3
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#if !ERROR_DEPRECATED
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/*
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* These registers were previously wrongly named. Provide previous definitions so
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* as not to break platforms that continue using them.
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*/
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#define CORTEX_A72_ACTLR CORTEX_A72_CPUACTLR_EL1
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#define CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH
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#define CORTEX_A72_ACTLR_NO_ALLOC_WBWA CORTEX_A72_CPUACTLR_EL1_NO_ALLOC_WBWA
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#define CORTEX_A72_ACTLR_DCC_AS_DCCI CORTEX_A72_CPUACTLR_EL1_DCC_AS_DCCI
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#endif /* !ERROR_DEPRECATED */
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#endif /* __CORTEX_A72_H__ */
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@ -1,14 +0,0 @@
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/*
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* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __SMCC_H__
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#define __SMCC_H__
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#if !ERROR_DEPRECATED
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#include <smccc.h>
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#endif
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#endif /* __SMCC_H__ */
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@ -57,17 +57,6 @@
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* does not equal SMC_UNK. This is to ensure that the caller won't mistake the
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* returned UUID in x0 for an invalid SMC error return
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*/
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#if !ERROR_DEPRECATED
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#define DEFINE_SVC_UUID(_name, _tl, _tm, _th, _cl, _ch, \
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_n0, _n1, _n2, _n3, _n4, _n5) \
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CASSERT((uint32_t)(_tl) != (uint32_t) SMC_UNK, invalid_svc_uuid);\
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static const uuid_t _name = { \
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_tl, _tm, _th, _cl, _ch, \
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{ _n0, _n1, _n2, _n3, _n4, _n5 } \
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}
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#endif
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#define DEFINE_SVC_UUID2(_name, _tl, _tm, _th, _cl, _ch, \
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_n0, _n1, _n2, _n3, _n4, _n5) \
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CASSERT((uint32_t)(_tl) != (uint32_t) SMC_UNK, invalid_svc_uuid);\
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@ -66,9 +66,6 @@
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#define SMC_32 U(0)
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#define SMC_TYPE_FAST ULL(1)
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#if !ERROR_DEPRECATED
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#define SMC_TYPE_STD ULL(0)
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#endif
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#define SMC_TYPE_YIELD ULL(0)
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#define SMC_OK ULL(0)
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@ -7,10 +7,6 @@
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#ifndef __UTILS_H__
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#define __UTILS_H__
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#if !ERROR_DEPRECATED
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#include <utils_def.h>
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#endif
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/*
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* C code should be put in this part of the header to avoid breaking ASM files
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* or linker scripts including it.
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@ -37,7 +37,6 @@ struct secure_partition_boot_info;
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/*******************************************************************************
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* Mandatory common functions
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******************************************************************************/
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unsigned long long plat_get_syscnt_freq(void) __deprecated;
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unsigned int plat_get_syscnt_freq2(void);
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int plat_get_image_source(unsigned int image_id,
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@ -55,16 +55,6 @@ func smc
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smc #0
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endfunc smc
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/* -----------------------------------------------------------------------
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* void zeromem16(void *mem, unsigned int length);
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*
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* Initialise a memory region to 0.
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* The memory address must be 16-byte aligned.
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* NOTE: This function is deprecated and zeromem should be used instead.
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* -----------------------------------------------------------------------
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*/
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.equ zeromem16, zeromem
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/* -----------------------------------------------------------------------
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* void zero_normalmem(void *mem, unsigned int length);
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*
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@ -1,9 +0,0 @@
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/*
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* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#if !ERROR_DEPRECATED
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#include "./aarch64/spinlock.S"
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#endif
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@ -128,12 +128,3 @@ func psci_power_down_wfi
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wfi
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no_ret plat_panic_handler
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endfunc psci_power_down_wfi
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/* -----------------------------------------------------------------------
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* void psci_entrypoint(void);
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* The deprecated entry point for PSCI on warm boot for AArch64.
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* -----------------------------------------------------------------------
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*/
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func_deprecated psci_entrypoint
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b bl31_warm_entrypoint
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endfunc_deprecated psci_entrypoint
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@ -19,9 +19,6 @@
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* platforms but may also be overridden by a platform if required.
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*/
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#pragma weak bl31_plat_runtime_setup
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#if !ERROR_DEPRECATED
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#pragma weak plat_get_syscnt_freq2
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#endif /* ERROR_DEPRECATED */
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#if SDEI_SUPPORT
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#pragma weak plat_sdei_handle_masked_trigger
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@ -51,25 +48,6 @@ unsigned int platform_core_pos_helper(unsigned long mpidr)
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return idx;
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}
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#if !ERROR_DEPRECATED
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unsigned int plat_get_syscnt_freq2(void)
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{
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WARN("plat_get_syscnt_freq() is deprecated\n");
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WARN("Please define plat_get_syscnt_freq2()\n");
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/*
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* Suppress deprecated declaration warning in compatibility function
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*/
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#pragma GCC diagnostic push
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#pragma GCC diagnostic ignored "-Wdeprecated-declarations"
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unsigned long long freq = plat_get_syscnt_freq();
|
||||
#pragma GCC diagnostic pop
|
||||
|
||||
assert(freq >> 32 == 0);
|
||||
|
||||
return (unsigned int)freq;
|
||||
}
|
||||
#endif /* ERROR_DEPRECATED */
|
||||
|
||||
#if SDEI_SUPPORT
|
||||
/*
|
||||
* Function that handles spurious SDEI interrupts while events are masked.
|
||||
|
|
|
|||
|
|
@ -28,27 +28,6 @@
|
|||
|
||||
#define MPIDR_RES_BIT_MASK 0xff000000
|
||||
|
||||
/* ------------------------------------------------------------------
|
||||
* int platform_get_core_pos(int mpidr)
|
||||
* Returns the CPU index of the CPU specified by mpidr. This is
|
||||
* defined when platform compatibility is disabled to enable Trusted
|
||||
* Firmware components like SPD using the old platform API to work.
|
||||
* This API is deprecated and it assumes that the mpidr specified is
|
||||
* that of a valid and present CPU. Instead, plat_my_core_pos()
|
||||
* should be used for CPU index of the current CPU and
|
||||
* plat_core_pos_by_mpidr() should be used for CPU index of a
|
||||
* CPU specified by its mpidr.
|
||||
* ------------------------------------------------------------------
|
||||
*/
|
||||
func_deprecated platform_get_core_pos
|
||||
bic x0, x0, #MPIDR_RES_BIT_MASK
|
||||
mrs x1, mpidr_el1
|
||||
bic x1, x1, #MPIDR_RES_BIT_MASK
|
||||
cmp x0, x1
|
||||
beq plat_my_core_pos
|
||||
b platform_core_pos_helper
|
||||
endfunc_deprecated platform_get_core_pos
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* Placeholder function which should be redefined by
|
||||
* each platform.
|
||||
|
|
|
|||
|
|
@ -26,44 +26,6 @@
|
|||
* --------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/* -------------------------------------------------------
|
||||
* unsigned long platform_get_stack (unsigned long mpidr)
|
||||
*
|
||||
* For the current CPU, this function returns the stack
|
||||
* pointer for a stack allocated in device memory. The
|
||||
* 'mpidr' should correspond to that of the current CPU.
|
||||
* This function is deprecated and plat_get_my_stack()
|
||||
* should be used instead.
|
||||
* -------------------------------------------------------
|
||||
*/
|
||||
func_deprecated platform_get_stack
|
||||
#if ENABLE_ASSERTIONS
|
||||
mrs x1, mpidr_el1
|
||||
cmp x0, x1
|
||||
ASM_ASSERT(eq)
|
||||
#endif
|
||||
b plat_get_my_stack
|
||||
endfunc_deprecated platform_get_stack
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* void platform_set_stack (unsigned long mpidr)
|
||||
*
|
||||
* For the current CPU, this function sets the stack pointer
|
||||
* to a stack allocated in normal memory. The
|
||||
* 'mpidr' should correspond to that of the current CPU.
|
||||
* This function is deprecated and plat_get_my_stack()
|
||||
* should be used instead.
|
||||
* -----------------------------------------------------
|
||||
*/
|
||||
func_deprecated platform_set_stack
|
||||
#if ENABLE_ASSERTIONS
|
||||
mrs x1, mpidr_el1
|
||||
cmp x0, x1
|
||||
ASM_ASSERT(eq)
|
||||
#endif
|
||||
b plat_set_my_stack
|
||||
endfunc_deprecated platform_set_stack
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* uintptr_t plat_get_my_stack ()
|
||||
*
|
||||
|
|
|
|||
|
|
@ -42,32 +42,6 @@ func plat_set_my_stack
|
|||
ret
|
||||
endfunc plat_set_my_stack
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* unsigned long platform_get_stack ()
|
||||
*
|
||||
* For cold-boot BL images, only the primary CPU needs a
|
||||
* stack. This function returns the stack pointer for a
|
||||
* stack allocated in device memory. This function
|
||||
* is deprecated.
|
||||
* -----------------------------------------------------
|
||||
*/
|
||||
func_deprecated platform_get_stack
|
||||
b plat_get_my_stack
|
||||
endfunc_deprecated platform_get_stack
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* void platform_set_stack ()
|
||||
*
|
||||
* For cold-boot BL images, only the primary CPU needs a
|
||||
* stack. This function sets the stack pointer to a stack
|
||||
* allocated in normal memory.This function is
|
||||
* deprecated.
|
||||
* -----------------------------------------------------
|
||||
*/
|
||||
func_deprecated platform_set_stack
|
||||
b plat_set_my_stack
|
||||
endfunc_deprecated platform_set_stack
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* Single cpu stack in normal memory.
|
||||
* Used for C code during boot, PLATFORM_STACK_SIZE bytes
|
||||
|
|
|
|||
|
|
@ -33,16 +33,6 @@ NEED_BL32 := yes
|
|||
# generated while the code is executing in S-EL1/0.
|
||||
TSP_NS_INTR_ASYNC_PREEMPT := 0
|
||||
|
||||
# If TSPD_ROUTE_IRQ_TO_EL3 build flag is defined, use it to define value for
|
||||
# TSP_NS_INTR_ASYNC_PREEMPT for backward compatibility.
|
||||
ifdef TSPD_ROUTE_IRQ_TO_EL3
|
||||
ifeq (${ERROR_DEPRECATED},1)
|
||||
$(error "TSPD_ROUTE_IRQ_TO_EL3 is deprecated. Please use the new build flag TSP_NS_INTR_ASYNC_PREEMPT")
|
||||
endif
|
||||
$(warning "TSPD_ROUTE_IRQ_TO_EL3 is deprecated. Please use the new build flag TSP_NS_INTR_ASYNC_PREEMPT")
|
||||
TSP_NS_INTR_ASYNC_PREEMPT := ${TSPD_ROUTE_IRQ_TO_EL3}
|
||||
endif
|
||||
|
||||
ifeq ($(EL3_EXCEPTION_HANDLING),1)
|
||||
ifeq ($(TSP_NS_INTR_ASYNC_PREEMPT),0)
|
||||
$(error When EL3_EXCEPTION_HANDLING=1, TSP_NS_INTR_ASYNC_PREEMPT must also be 1)
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue