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Documentation: Fix broken links in ToCs

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Change-Id: I4fcdb8e813e0392c2cd3d0623698e8319b3b0593
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Sandrine Bailleux 2016-01-08 14:12:55 +00:00
parent de849c8c4f
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4
docs/firmware-design.md
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@ -8,7 +8,7 @@ Contents :
3. [EL3 runtime services framework](#3--el3-runtime-services-framework) 3. [EL3 runtime services framework](#3--el3-runtime-services-framework)
4. [Power State Coordination Interface](#4--power-state-coordination-interface) 4. [Power State Coordination Interface](#4--power-state-coordination-interface)
5. [Secure-EL1 Payloads and Dispatchers](#5--secure-el1-payloads-and-dispatchers) 5. [Secure-EL1 Payloads and Dispatchers](#5--secure-el1-payloads-and-dispatchers)
6. [Crash Reporting in BL31](#6--crash-reporting-in-bl3-1) 6. [Crash Reporting in BL31](#6--crash-reporting-in-bl31)
7. [Guidelines for Reset Handlers](#7--guidelines-for-reset-handlers) 7. [Guidelines for Reset Handlers](#7--guidelines-for-reset-handlers)
8. [CPU specific operations framework](#8--cpu-specific-operations-framework) 8. [CPU specific operations framework](#8--cpu-specific-operations-framework)
9. [Memory layout of BL images](#9-memory-layout-of-bl-images) 9. [Memory layout of BL images](#9-memory-layout-of-bl-images)
@ -1455,7 +1455,7 @@ images. The platform policy can be modified to allow additional images.
11. Use of coherent memory in Trusted Firmware 11. Use of coherent memory in Trusted Firmware
---------------------------------------------- -----------------------------------------------
There might be loss of coherency when physical memory with mismatched There might be loss of coherency when physical memory with mismatched
shareability, cacheability and memory attributes is accessed by multiple CPUs shareability, cacheability and memory attributes is accessed by multiple CPUs

16
docs/firmware-update.md
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@ -3,11 +3,11 @@ ARM Trusted Firmware - Firmware Update Design Guide
Contents : Contents :
1. [Introduction](#1-introduction) 1. [Introduction](#1--introduction)
2. [FWU Overview](#2-fwu-overview) 2. [FWU Overview](#2--fwu-overview)
3. [Image Identification](#3-image-identification) 3. [Image Identification](#3--image-identification)
4. [FWU State Machine](#4-fwu-state-machine) 4. [FWU State Machine](#4--fwu-state-machine)
5. [SMC Interface](#5-smc-interface) 5. [BL1 SMC Interface](#5--bl1-smc-interface)
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
@ -36,7 +36,7 @@ the TBBR.
2. FWU Overview 2. FWU Overview
--------------- ----------------
The FWU boot flow is primarily mediated by BL1. Since BL1 executes in ROM, and The FWU boot flow is primarily mediated by BL1. Since BL1 executes in ROM, and
it is usually desirable to minimize the amount of ROM code, the design allows it is usually desirable to minimize the amount of ROM code, the design allows
@ -74,7 +74,7 @@ use all defined FWU images. Other platforms may use a subset of these.
3. Image Identification 3. Image Identification
----------------------- ------------------------
Each FWU image and certificate is identified by a unique ID, defined by the Each FWU image and certificate is identified by a unique ID, defined by the
platform, which BL1 uses to fetch an image descriptor (`image_desc_t`) via a platform, which BL1 uses to fetch an image descriptor (`image_desc_t`) via a
@ -135,7 +135,7 @@ The following is a brief description of the supported states:
5. BL1 SMC Interface 5. BL1 SMC Interface
----------------- ---------------------
### BL1_SMC_CALL_COUNT ### BL1_SMC_CALL_COUNT

2
docs/interrupt-framework-design.md
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@ -10,7 +10,7 @@ Contents :
- [Valid Routing Models](#113-valid-routing-models) - [Valid Routing Models](#113-valid-routing-models)
+ [Secure-EL1 Interrupts](#1131-secure-el1-interrupts) + [Secure-EL1 Interrupts](#1131-secure-el1-interrupts)
+ [Non-secure Interrupts](#1132-non-secure-interrupts) + [Non-secure Interrupts](#1132-non-secure-interrupts)
+ [EL3 interrupts](#1133-el3_interrupts) + [EL3 interrupts](#1133-el3-interrupts)
- [Mapping of Interrupt Type to Signal](#114-mapping-of-interrupt-type-to-signal) - [Mapping of Interrupt Type to Signal](#114-mapping-of-interrupt-type-to-signal)
+ [Effect of mapping of several interrupt types to one signal](#1141-effect-of-mapping-of-several-interrupt-types-to-one-signal) + [Effect of mapping of several interrupt types to one signal](#1141-effect-of-mapping-of-several-interrupt-types-to-one-signal)
- [Assumptions in Interrupt Management Framework](#12-assumptions-in-interrupt-management-framework) - [Assumptions in Interrupt Management Framework](#12-assumptions-in-interrupt-management-framework)